Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs

Cho, Seongjae; Kang, In Man; Kim, Kyung Rok

doi:10.1587/elex.7.1499

Cited by 4 publications

(1 citation statement)

References 5 publications

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“…In the other JNTs, the surface of the nanowire is still depleted at V G =1V, which results in a significant lower gate capacitance. The gate charge needs to switch a device on being It is interesting to note that, in some cases, C gd can be zero or even negative in JNTs, due to the particularly low DIBL effect (13). This gives rise to a very low Miller capacitance, which might be of great interest for RF applications.…”

Section: Gate Capacitancementioning

confidence: 99%

A Simulation Comparison between Junctionless and Inversion-Mode MuGFETs

et al. 2011

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A new type of multigate MOSFET, called the junctionless nanowire transistor (JNT), has recently been proposed. It avoids junction formation problem and can be used to make very short-channel devices. Here, we compare the properties and performances of junctionless nanowire transistors with those of with Π-gate inversion-mode (IM) devices. The performances of silicon JNTs and IM transistors are evaluated in terms of short-channel effects, current drive, and gate capacitance. Junctionless devices are shown to have smaller short-channel effects than inversion-mode transistors with junctions. Comparison of carrier transport in the channel is made between junctionless nanowires and inversion-mode multigate field-effect transistors, and the benefits/drawbacks of bulk transport vs. surface transport are addressed.

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Section: Gate Capacitancementioning

confidence: 99%