Investigation of stepwise charging circuits for power-clock generation in Adiabatic Logic

Raghav, Himadri Singh; Bartlett, V.A.; Kale, I.

doi:10.1109/prime.2016.7519499

Cited by 12 publications

(5 citation statements)

References 14 publications

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“…Adiabatic logic requires a specialized power supply scheme, typically sinusoidally [23] varying power rails in order to enable computation, although trapezoidal [33] and stepwise charging [25] power-clocks also exist. Stepwise Charging Circuit (SCC) power-rails can be energy-efficient, especially if we use more steps [24], however, an increased number of steps tends to increase energy cost again due to the circuit overheads associated with the control signals managing the corresponding capacitors [27]. In our case we are using a sinusoidal, LC-based power clock with a by-pass nMOS switch, M P C entraining the LC circuit formed by the combination of our PC inductor, L P C , equalising capacitor C E and load capacitance C L (itself a combination of parasitics + the capacitances of active synapses) and compensating for natural energy losses in the system.…”

Section: A Powering the Adiabatic Capacitive Neuronsmentioning

confidence: 99%

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

Maheshwari

Serb

Papavassiliou

et al. 2022

IEEE Trans. Circuits Syst. I

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In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with 'memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 o C across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

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Section: A Powering the Adiabatic Capacitive Neuronsmentioning

confidence: 99%

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

Maheshwari

Serb

Papavassiliou

et al. 2022

IEEE Trans. Circuits Syst. I

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“…Different approaches for generating such signals have already been investigated, such as resonant circuits or switched capacitors. 14,15 Figure 5. Electrical diagram of the four cascaded buffers considered in this section.…”

Section: Cascaded Buffersmentioning

confidence: 99%

Contactless capacitive adiabatic logic

Perrin

Galisultanov

Samaali

et al. 2017

Nanoengineering: Fabrication, Properties, Optics, and Devices XIV

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CMOS technology allows a femto Joule energy dissipation per logic operation, if operated at optimal frequency and voltage. However, this value remains orders of magnitude above the theoretical limit predicted by Landauer. In this work, we present a new paradigm for low power computation, based on variable capacitors. Such components can be implemented with existing MEMS technologies. We show how a smooth capacitance modulation allows an energy-efficient transfer of information through the circuit. By removing electrical contacts, our method limits the current leakages and the associated energy loss. Therefore, capacitive logic must be able to achieve extremely low power dissipation when driven adiabatically. Contactless capacitive logic also promises a better reliability than systems based on MEMS nanorelays.

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“…inductorbased example from [18]. Capacitive PCs can be energyefficient, especially if we use more steps [22], however, as the step increases the switches also tend to increase linearly thereby increasing the energy cost [17]]. Thus, we chose the sinusoidal, inductor-based PC shown in Fig.…”

Section: A Power-clock Generator Designmentioning

confidence: 99%

An Adiabatic Regenerative Capacitive Artificial Neuron

Maheshwari

Serb

Papavassiliou

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1M Hz indicates a ≈ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, nonregenerative ones, which translates into a ≈ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.

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Investigation of stepwise charging circuits for power-clock generation in Adiabatic Logic

Cited by 12 publications

References 14 publications

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

Contactless capacitive adiabatic logic

An Adiabatic Regenerative Capacitive Artificial Neuron

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