Investigation on junctionless floating body DRAMs including Trap Assisted Tunneling

Giusi, G.

doi:10.1016/j.sse.2020.107799

Cited by 2 publications

(2 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A different number of 1T-DRAM approaches have been recently reported in the literature [2][3][4][5][6][7]. In Floating Body 1T-DRAMs (FB-DRAMs) [8][9][10][11][12][13][14][15], the information is encoded as non-equilibrium excess charge (typically holes) stored in the bulk of a Silicon On Insulator MOSFET. The advantage of FB-DRAMs with respect to other 1T-DRAM architectures is the higher compatibility with the standard Silicon technology, especially in the cases of embedded systems or systems on chip.…”

Section: Introductionmentioning

confidence: 99%

“…In particular the SRH recombination rate increases with the product of the electron-hole concentrations (np) and reduces with the increase of the recombination lifetime τ. Several new devices, with different materials and/or different architectures, have been proposed to increase the retention time [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. In this work we focus on the architectural approach, maintaining the Silicon as the active material.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Floating Body DRAM with Body Raised and Source/Drain Separation

Giusi

2021

Electronics

Self Cite

View full text Add to dashboard Cite

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

show abstract