Investigation on Stability of p-GaN HEMTs With an Indium–Tin–Oxide Gate Under Forward Gate Bias

Chang, Chih-Yao; Shen, Yao-Luen; Wang, Ching-Yao; Tang, Shun-Wei; Wu, Tian-Li; Kuo, Wei-Hung; Lin, Suh-Fang; Huang, Chih-Fang

doi:10.1109/jeds.2021.3096389

Cited by 4 publications

(3 citation statements)

References 18 publications

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“…However, for the traditional thick gate metal, it is difficult to precisely monitor the breakdown points and the temperature distribution when the devices are stressed by high power, which hinders the research of the device’s reliability [ 22 , 23 , 24 ]. We note that Wu et al suggested using indium tin oxide (ITO) instead of the traditional Schottky metal to improve the breakdown voltage of the gate [ 25 , 26 , 27 ].…”

Section: Introductionmentioning

confidence: 99%

Investigating the Failure Mechanism of p-GaN Gate HEMTs under High Power Stress with a Transparent ITO Gate

Han

Wang

et al. 2023

Micromachines

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The channel temperature distribution and breakdown points are difficult to monitor for the traditional p-GaN gate HEMTs under high power stress, because the metal gate blocks the light. To solve this problem, we processed p-GaN gate HEMTs with transparent indium tin oxide (ITO) as the gate terminal and successfully captured the information mentioned above, utilizing ultraviolet reflectivity thermal imaging equipment. The fabricated ITO-gated HEMTs exhibited a saturation drain current of 276 mA/mm and an on-resistance of 16.6 Ω·mm. During the test, the heat was found to concentrate in the vicinity of the gate field in the access area, under the stress of VGS = 6 V and VDS = 10/20/30 V. After 691 s high power stress, the device failed, and a hot spot appeared on the p-GaN. After failure, luminescence was observed on the sidewall of the p-GaN while positively biasing the gate, revealing the side wall is the weakest spot under high power stress. The findings of this study provide a powerful tool for reliability analysis and also point to a way for improving the reliability of the p-GaN gate HEMTs in the future.

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Section: Introductionmentioning

confidence: 99%

Investigating the Failure Mechanism of p-GaN Gate HEMTs under High Power Stress with a Transparent ITO Gate

Han

Wang

et al. 2023

Micromachines

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“…In order to improve the p-GaN etching process as well as the device performance, a 10 nm u-GaN was designed as an etching buffer layer to be inserted in the p-GaN/AlGaN/GaN HEMT epi structure. In this work, the p-GaN gate HEMT with indium-tin-oxide (ITO) gate electrode 23,24) was fabricated on two epi structures with and without the u-GaN etching buffer layer inserted. The DC characteristics and simulation were investigated and the statistical data in the two cases were compared.…”

mentioning

confidence: 99%

“…The p-GaN HEMTs devices were fabricated by the gate-first process, where the detailed fabrication procedure has been described in our previous studies. 23,24) Figures 1(a) and 1(b) show the schematics of the cross-section view for the fabricated p-GaN HEMT on the epi structure without and with the u-GaN etching buffer layer. The devices have a gate-width (W g ) of 110 μm, a gate-length (L g ) of 3 μm, a gate-drain distance (L gd ) of 15 μm, and a gate-source distance (L gs ) of 5 μm.…”

mentioning

confidence: 99%

Process improvement of p-GaN HEMTs with a u-GaN etching buffer layer inserted

Chang¹,

Shen²,

Tang³

et al. 2022

Appl. Phys. Express

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In this study, a 10-nm u-GaN etching buffer layer was designed and inserted into the standard p-GaN/AlGaN/GaN HEMT structure to improve the p-GaN etching process. The experimental result shows that the device with the u-GaN layer can avoid the over-etched issue, further improving the uniformity of the etching profile and the ON-resistance of the devices. The simulation result indicates that the drain current would slightly increase due to reduced conduction band raising when the u-GaN layer is inserted. In sum, the process uniformity can improve when the u-GaN layer is inserted and in the meantime, excellent device characteristics are maintained.

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High Threshold Voltage Enhancement-Mode Regrown p-GaN Gate HEMTs With a Robust Forward Time-Dependent Gate Breakdown Stability

Tang

Huang

Chen

et al. 2022

IEEE Electron Device Lett.

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Investigation on Stability of p-GaN HEMTs With an Indium–Tin–Oxide Gate Under Forward Gate Bias

Cited by 4 publications

References 18 publications

Investigating the Failure Mechanism of p-GaN Gate HEMTs under High Power Stress with a Transparent ITO Gate

Investigating the Failure Mechanism of p-GaN Gate HEMTs under High Power Stress with a Transparent ITO Gate

Process improvement of p-GaN HEMTs with a u-GaN etching buffer layer inserted

High Threshold Voltage Enhancement-Mode Regrown p-GaN Gate HEMTs With a Robust Forward Time-Dependent Gate Breakdown Stability

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