Investigations of performance enhancement in a poly-Si nanowire FET featuring independent double-gated configuration and its nonvolatile memory applications

Abstract

Charge-trapping SONOS devices featuring nanowire (NW) and independent double-gated (IDG) structure are fabricated and characterized. The mechanism leading to DG output current performance enhancement is investigated. Taking advantage of the separated-gated property, the back-gate bias effect is used to probe its impacts on programming efficiency. It is also discovered that reduced NW thickness leads to stronger back-gate effects.