Investigations of Power Analysis Attacks and Countermeasures for ARIA

Yoo, HyungSo; Herbst, Christoph; Mangard, Stefan; Oswald, Elisabeth; Moon, SangJae

doi:10.1007/978-3-540-71093-6_13

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…ARIA is known to be relatively strong against differential crypto-analysis and linear crypto-analysis [6]. Investigations of power analysis attacks and countermeasures for ARIA can be found in [7]- [9]. However, only a small number of papers have been published on the hardware architecture for the ARIA algorithm in contrast to AES.…”

Section: Related Workmentioning

confidence: 99%

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High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

2008

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This paper presents two types of high‐speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area‐throughput trade‐offs are evaluated depending on the S‐box implementation by using look‐up tables or combinational logic which involves composite field arithmetic. The sub‐pipelined architectures for non‐feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S‐box implementation using composite field arithmetic over GF(24)2, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 μm CMOS technology. This is the first sub‐pipelined architecture of ARIA for high throughput to date.

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Section: Related Workmentioning

confidence: 99%

“…Figure 1 shows how the S-box can be designed using GF(2 4 ) arithmetic, as described in (7). Figure 1(a) shows the S-box function, which is composed of the inversion over GF (2 8 ) and the affine transformation, here denoted by Affine(x).…”

Section: Detailed Hardware Architecture Of the Primitives 1 Submentioning

confidence: 99%

High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

2008

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Physical Attack Countermeasures for Reconfigurable Cryptographic Processors

Liu

Wang

Wei

2018

Reconfigurable Cryptographic Processor

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Four-factor verification methodology for entity authentication assurance

Jeon¹

2011

2011 International Conference on Information Science and Applications

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In this age of the accelerated globalization and the increased mobile population, various methods of wire/wireless communication technologies and their service are converged and integrated each other as Internet Technology has been developing. As a result, functions of the devices such as a computer, a digital device, a mobile device and a smart phone have been evolving. At present, there are different types of ID card that replace the personal identification based on contact/contactless IC card. Currently, various security protocols for users' authentication are being widely and mixedly used. However, current technology is unable to guarantee the entities (human and devices) authentication assurance due to an abuse caused by loss, theft and fabrication. Therefore, a new authentication policy is needed in order to assure the authentication for both users and devices. In this paper, I propose a new framework that guarantees the authentication assurance of wire/wireless entities such as humans and devices by using proposed four-factor authentication methodologies which can provide enhanced security, efficient policy of entity authentication assurance and efficient operation.

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Investigations of Power Analysis Attacks and Countermeasures for ARIA

Cited by 3 publications

References 10 publications

High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

Physical Attack Countermeasures for Reconfigurable Cryptographic Processors

Four-factor verification methodology for entity authentication assurance

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