Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

Abstract

In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the crosscorrelation of two edges depends on the fabrication process. Based on the improved simulation method proposed in the Part I of this paper, the impacts of correlated LER/LWR in the channel of double-gate devices are investigated. The results show that V th distribution strongly relies on cross-correlation, and can exhibit non-Gaussian distribution and/or multipeak distribution, which enlarges the V th variation.

Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS

“…NS_Total is the total mismatch contribution of sidewall and top-bottom surface roughness in NSFET. NS_Total for uncorrelated LER is given by the following equation [13], [16]: NS_Total = ()…”

“…However, deformation inside the gate region significantly changes device performance [29]. In this work, we have taken a generalized 3-D LER roughness profile in NW and NS-FETs for the worst-case LER scenario [13], [20].…”

Flash gate optimized process and integration for electrical performances requirement on advanced embedded memory

“…A deep analysis helped to highlight a 10nm spread of the memory gate CD on the same WL. This spread can be assimilated to a Line Width Roughness (LWR) issue [2], [3].…”

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I–Modeling and Simulation Method

“…Section III is dedicated to an improved statistical simulation method based on original Fourier synthesis method [14], which can be used to generate LER sequences with nonzero correlation coefficient. The simulation results are discussed in Section IV and conclusions are drawn in Section V. As will be further investigated in the Part II of this paper [25], experimental results will show the correlated LER phenomenon in Fin and nanowire channel LERs fabricated by different processes. And the statistical simulation of double gate devices will also be performed based on an improved simulation method proposed in the Part I of the paper, which demonstrates the impacts of correlated LERs on devices.…”