Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I–Modeling and Simulation Method

Abstract

In this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated. Based on the characterization methodology of autocorrelation functions (ACF), a new theoretical model of LWR is proposed, which indicates that the LWR ACF is composed of two parts: one involves LER information; the other involves the cross-correlation of the two edges. Additional characteristic parameters for LER/LWR are proposed to represent the missing cross-correlation information in conventional approaches of LER/LWR description, other than LER/LWR amplitude and auto-correlation length. An improved simulation method forcorrelated LERs is also proposed, which can provide helpful guidelines for the characterization, modeling, and the optimization of LER/LWR in nanoscale CMOS technology. The experimental results and device simulation results are discussed in detail in the part II of this paper.

Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

“…Based on the improved simulation method proposed in the Part I of this paper [14], correlated LER pairs are generated and inputted into Synopsys Sentaurus [22] for device simulation. LER properties of two edges, namely amplitude and auto-correlation length , are set as equal, which fits typical experimental observations.…”

“…Part I of this paper [14] introduces a new theoretical model to describe the correlation between LER and LWR, based on the characterization methodology of auto-correlation function (ACF) [3]. The model indicates that LWR ACF has two components: one is LER ACF and the other is LER cross-correlation function (CCF).…”

Line-Edge Roughness from Extreme Ultraviolet Lithography to Fin-Field-Effect-Transistor: Computational Study

“…In this sense, it is required to understand LER creation mechanism in EUVL and FinFET performance degradation due to LER [23,24]. Although many studies have determined LER effects of EUVL and FinFETs [25,26], this paper deals with LER effects of EUVL simulation parameters for 5-nm pattern formation and FinFET performance with 5-nm gate length, totally describing LER effects from EUVL processes to FinFET devices. For LER creation in EUVL and LER impacts on FinFET performance, a LER modeling in EUVL processes and an analytical method for FinFET degradation due to LER are described, respectively.…”

Electronic transport in graphene nanoribbons with correlated line-edge roughness

“…LER inherent to top-down methods of producing GNRs are investigated extensively in the literature [8,[14][15][16][17][18][19][20][21], but in all studies, roughnesses of the two edges have been independently treated and the cross-correlation between them has been neglected. The importance of cross-correlation between the roughnesses of surfaces in Si Fin, nanowires, and quantum wells has been addressed in previous studies [22][23][24]. The role of cross-correlation between GNR edges cannot be ignored in many cases, especially in GNRs that are produced by unzipping carbon nanotubes where both LER at both edges are fully correlated.…”