Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.

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The thin-film formation of the spin coating is one of the important factors in the fabrication of microelectronic devices. In this study, the theoretical models for thickness variation during spin coating and nanotopography impact are analyzed. The finite-difference-time-domain method and the finite-element method are used to solve the convective diffusion equation for solvent distribution and the Navier-Stokes equation including solvent evaporation for the film thickness change. These numerical calculations are in good agreement with experimental results for 193 nm chemically amplified resist ͑CAR͒ and i-line non-CAR resists. Solvent distributions of nonspin coating are described through mesoscale modeling by using the Monte Carlo method. Nanotopography impact on the variation of resist distribution after spin coating is investigated quantitatively. The reason for the similarity in the transfer functions for different types of wafers is due to solvent diffusion and evaporation.

In the semiconductor lithography process, the thermal flow process after development resolves the patterning of sub-100-nm contact holes and the cost problem of resolution-enhancement technology. In this study, resist flowing behavior and contact hole shrinkage are described by using the thermal reflow length of the boundary-movement method and the analysis of image process. The viscosity variable affects the shrinkage of critical dimensions. This variable is extracted from the experimental data by using a proposed equation. These results agree well with the experimental results in both contact hole size and the vertical wall of profile according to the baking temperature and time. Although the most effective process of the 193-nm chemically amplified resist is the postexposure bake process for critical dimension, the parameter of the development process-the inhibition reaction order of the enhanced Mack model-is shown as the most controllable parameter for critical dimension in the thermal reflow process.

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