(Invited) Doping Considerations for Finfet, Gate-All-Around, and Nanosheet Based Devices

Abstract

The IEEE International Roadmap for Devices and Systems (IRDS) for More Moore devices summarises the Logic Device state of play very effectively; the FinFET is the key device architecture that could enable logic device scaling until 2025. Increasing fin height while reducing number of fins at unit footprint area is an effective solution to improve performance. It is forecasted that the parasitics will remain as a dominant term in the performance of critical paths. For reduced supply voltage, a transition to gate-all-around (GAA) structures such as lateral nanowires or nanosheets will be necessary to improve electrostatics. Lateral GAA structure would eventually evolve in to the vertical GAA structure to gain back the performance loss due to increasing parasitics at tighter pitches. In this paper we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion for these device technologies.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

“…The SiGe cladded nanosheet increased hole mobility and reduced V T . Additionally, this group later achieved a highly compressive strain in the SiGe cladded nanosheet channel by adjusting the thickness of the cladded SiGe layer and the Ge content [211]. A further improvement in hole mobility and channel resistance reduction were observed.…”