(Invited) Gate Stack Technologies for SiC Power MOSFETs

Abstract

Silicon carbide has gained considerable attention for future power electronics. However, it's well known that SiC-based MOS devices have suffered from degraded electrical properties of thermally grown SiO2/SiC interfaces, such as low inversion carrier mobility and deteriorated gate oxide reliability. This paper overviews the fundamental aspects of SiC-MOS devices and indicates intrinsic obstacles connected with an accumulation of both negative fixed charges and interface defects and with a small conduction band offset of the SiO2/SiC interface which leading to the increased gate leakage current of MOS devices. To overcome these problems, we proposed using aluminum oxynitride (AlON) insulators stacked on thin SiO2 underlayers for SiC-MOS devices. Superior flatband voltage stability of AlON/SiO2/SiC gate stacks was achieved by optimizing the thickness of the underlayer and nitrogen concentration in the high-k dielectrics. Moreover, we demonstrated reduced gate leakage current and improved current drivability of SiC-MOSFETs with AlON/SiO2 gate stacks.

Band alignment between 4H-SiC and atomic-layer-deposited ZrO2determined by X-ray photoelectron spectroscopy

“…The utilization of stacked gate dielectric technology could be effective in reducing the abovementioned gate leakage while maintaining a reasonably high gate dielectric constant. 7,21) Moreover, the results shown in Table I are very close to the values reported by Afanas'ev et al 11,12) However, when compared with the theoretical values predicted by charge neutrality level (CNL) method, 22,23) obvious differences are found. This could be ascribed to the less-accurate electron affinity of oxides utilized during the predications.…”

Defect engineering in SiC technology for high-voltage power devices

“…SiC MOS interface defects have been a long-standing problem in this community, and a number of review papers have been published on this subject. [143][144][145][146][147][148][149][150][151][152][153] Regarding the gate dielectric, SiO 2 has been almost exclusively investigated, even though AlON also shows promise. 154) Because SiC has a wide bandgap of 3.26 eV at room temperature, the choice of gate dielectric is very limited because a bandgap of higher than about 8 eV is required to ensure large band offsets at the conduction band and valance band sides with respect to SiC.…”

“…These trends indicate that regardless of the gate stack structure and fabrication process, the oxide/SiC interface is an oxidation front, and hence, an understanding of fundamental aspects of SiC oxidation is indispensable for further development of advanced SiC power MOSFETs. [143][144][145][146][147][148][149][150][151][152][153] The general expression of SiC oxidation can be separated into the following three reactions depending on oxidation conditions such as temperature and partial pressures of oxidant and byproducts:…”

Defect Profiling of Oxide‐Semiconductor Interfaces Using Low‐Energy Muons

“…This concentration is higher than expected for the n‐type SiC even in the case of upward band‐bending caused by thermal oxidation. [ 56 ] Therefore, we attribute the increase of F D at 260 K to the presence of electrons from the interface trap states.…”