(Invited) Low Temperature Direct Bonding 3D Stacking Technologies for High Density Device Integration

Cioccio, L. Di; Radu, Ionut; Gaudin, G.; Lacave, Thomas; Baudin, Floriane; Sadaka, Mariam; Signamarcheix, T.

doi:10.1149/05809.0017ecst

Cited by 5 publications

(1 citation statement)

References 8 publications

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“…Copper oxide bonding employing standard damascene process is a top candidate in 3D integration schemes and successful bonding is reported (1)(2)(3). Some of the main challenges in this technology are the dishing of the copper pads, the oxide erosion and the bonding accuracy, which are difficult to control and optimize as the wafer size increases and the device size decreases.…”

Section: Introductionmentioning

confidence: 99%

Copper Oxide Direct Bonding of 200mm CMOS Wafers with Five Metal Levels and TSVs: Morphological and Electrical Characterization

Cavaco¹,

Peng²,

Lavizzari³

et al. 2016

ECS Trans.

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We report for the first time complete data on 200mm wafer to wafer aligned copper oxide direct bonding of wafers with five metal levels each with through-silicon-vias (TSVs) as backside connection. Both surface acoustic microscope (SAM) and cross-section scanning electron microscope (X-SEM) images taken across the bonded wafer pairs evidence the good bonding quality of the resulting interface. Kelvin structures and daisy chains with up to 2500 copper to copper bonded pads are shown to be connected successfully and its resistance value to match a target value.

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Section: Introductionmentioning

confidence: 99%

Copper Oxide Direct Bonding of 200mm CMOS Wafers with Five Metal Levels and TSVs: Morphological and Electrical Characterization

Cavaco¹,

Peng²,

Lavizzari³

et al. 2016

ECS Trans.

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A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits

Koneru

Kannan

Chakrabarty

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits

Koneru

Kannan²,

Chakrabarty

2017

J. Emerg. Technol. Comput. Syst.

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Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not used in the fabrication of conventional integrated circuits (ICs). Therefore, a detailed analysis of the M3D fabrication process is required to understand the impact of defects that are likely to occur during chip fabrication. In this article, we first analyze electrostatic coupling in M3D ICs, which arises due to the aggressive scaling of the interlayer dielectric (ILD) thickness. We then analyze defects that arise due to voids created during wafer bonding, a key step in most M3D fabrication processes. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D IC. We also show that wafer-bonding defects can lead to a change in the resistance of interlayer vias (ILVs), and in some cases lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays using HSpice simulations. We study their impact on the effectiveness of delay-test patterns for multiple instances of IWLS 2005 benchmarks in which these defects were randomly injected. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm. Therefore, for such M3D ICs, test-generation methods must be enhanced to take M3D fabrication defects into account.

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(Invited) Low Temperature Direct Bonding 3D Stacking Technologies for High Density Device Integration

Abstract: 3D integration aims at providing highly integrated systems by vertically stacking and connecting various materials, technologies, and functional components together. We will review the different approaches, using direct bonding, developed to address 3D devices manufacturing challenges.

Cited by 5 publications

References 8 publications

Copper Oxide Direct Bonding of 200mm CMOS Wafers with Five Metal Levels and TSVs: Morphological and Electrical Characterization

Copper Oxide Direct Bonding of 200mm CMOS Wafers with Five Metal Levels and TSVs: Morphological and Electrical Characterization

A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits

Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits

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