Bonding energy represents an important parameter for direct bonding applications as well as for the elaboration of physical mechanisms at bonding interfaces. Measurement of bonding energy using double cantilever beam (DCB) under prescribed displacement is the most used technique thanks to its simplicity. The measurements are typically done in standard atmosphere with relative humidity above 30%. Therefore, the obtained bonding energies are strongly impacted by the water stress corrosion at the bonding interfaces. This paper presents measurements of bonding energies of directly bonded silicon wafers under anhydrous nitrogen conditions in order to prevent the water stress corrosion effect. It is shown that the measurements under anhydrous nitrogen conditions (less than 0.2 ppm of water in nitrogen) lead to high stable debonding lengths under static load and to higher bonding energies compared to the values measured under standard ambient conditions. Moreover, the bonding energies of Si/SiO2 or SiO2/SiO2 bonding interfaces are measured overall the classical post bond annealing temperature range. These new results allow to revisit the reported bonding mechanisms and to highlight physical and chemical phenomena in the absence of stress corrosion effect.

An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.Bonding of metal surfaces is extensively used for MEMS sealing, power devices, heat dissipation or 3D interconnections. For these applications, techniques such as thermo compression, with or without eutectic alloys or adhesives layers, bumps with low temperature solders or direct bonding are extensively implemented techniques. 1-7 Moreover, for More Moore and More than Moore applications, low temperature bonding and metal bonding are becoming the main drivers of the latest developments. As copper is the main metal used for CMOS interconnects, a high-density Cu interconnection between layer structures, is expected for future three-dimensional integration of electronic devices fabricated on the basis of different technology/ design concepts. In this paper, an overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD and TEM analysis. Dedicated characterization techniques for such bonding are presented. Hybridization Techniques ReviewCopper is the most (compared to other possible bonding metals) promising candidate for 3D integration technology either for TSV filling or interstata hybridizing. The main reasons of this choice is the widely use of copper in semiconductor device industries and the cost of ownership. On the other hand, the choice of the metal bonding technique is still an open question. Bonding anneal temperature, duration of the annealing, need of an underfill, size and pitch of the interconnect pads, availability of the technique for wafer bonding or die bonding are key parameters of the final choice. The main studied bonding techniques can be divided into two groups: with and without thermal compression.Bonding with a compression force: Diffusion bonding.-The thermal compression bonding is a well known technique. 8-10 Wafers or dies are pressed together with a controlled force in a bonding tool, while heating is applied (400 C) to allow the bonding diffusion mechanism. Thanks to the compression force, the surfaces roughness is not a limiting factor as the surface asperities are deformed at the bonding interface, therefore surfaces with a roughness in the range of 5 nm can be used. Copper oxide should be avoided or removed right before ...

Transfer of GaAs layers onto Si by helium and/or hydrogen implantation and wafer bonding was investigated. The optimum conditions for achieving blistering/splitting only after postimplantation annealing were experimentally obtained. It was found that specific implantation conditions induce large area exfoliation instead of blistering after annealing of unbonded GaAs. This effect is related to a narrow size and/or a depth distribution of the platelets in as-implanted GaAs and their evolution with annealing. The influence of substrate orientation in blistering/splitting of GaAs was also investigated. Thin GaAs layers were transferred onto silicon by a combination of He and/or H implantation, wafer bonding and low temperature annealing.

A systematic investigation of surface blister formation on GaN epitaxial layers implanted with 100 keV H 2 + ions with a dose of 1.3×10 17 cm -2 and annealed at various temperatures in the range of 350−700 °C was carried out. Two different activation energies were found for the formation of surface blisters: 1.79 eV in the lower temperature regime of 350-400 °C and 0.48 eV in the higher temperature regime of 400-700 °C. The depth and width of the blisters were determined using a stylus profilometer. The hydrogen implantation-induced damage was assessed using cross-sectional transmission microscopy revealing a band of defects extending from 230-500 nm from the surface of GaN.1 Introduction GaN and related nitrides have a wide range of applications in the area of optoelectronics as well as high frequency, high power electronic devices. These nitrides are mostly grown epitaxially on lattice and thermal mismatched substrates like sapphire, SiC or even on Si due to the fact that free-standing bulk GaN substrates are very expensive and are mostly available in small sizes [1,2]. The heteroepitaxial growth of GaN on foreign substrates leads to the formation of growth-related defects like dislocations, stacking faults, twins etc. that occur to relax the strain. The high density of dislocations in the epitaxial layers of GaN grown on hetero-substrates has deleterious effects on the performance and reliability of the devices fabricated utilising these layers. One of the methods to fabricate low-cost and high structural quality substrates, comparable to free-standing GaN substrates, for the epitaxial growth of group-III nitrides would be direct wafer bonding and layer transfer of thin GaN films via a high dose hydrogen implantation and layer splitting upon annealing [3,4]. The free-standing GaN substrate can be utilised to transfer multiple layers on other substrates. This process is based upon the agglomeration of hydrogen implantation-induced platelets upon annealing and the subsequent formation of overpressurized microcracks. For the case of the implanted wafer bonded to a handle wafer, splitting of a thin slice of material parallel to the bonding interface occurs [3, 5−7]. For this process to occur a narrow parameter window of implantation dose, annealing temperature and time has to be defined since the layer splitting is a strongly material dependent process. The physical mechanisms leading to the process of layer splitting can be conveniently investigated by studying the development of surface blisters in hydrogen implanted and annealed but unbonded wafers [7,8]. In the present investigation we have performed a systematic study of the formation of surface blisters on hydrogen implanted and annealed GaN layers grown epitaxially on sapphire.

A model of the defect formation at the bonding interface upon annealing in silicon wafer bonding is proposed in this paper. It is shown that the formation of the bonding defects depends on the thickness of the silicon oxide at the bonding interface. A mechanism of thermal voids formation is suggested based on the hydrogen solubility in amorphous silicon oxide. The interface gas quantity for various thicknesses of the buried oxide is predicted and good correlation with the experimental data is obtained.