An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.Bonding of metal surfaces is extensively used for MEMS sealing, power devices, heat dissipation or 3D interconnections. For these applications, techniques such as thermo compression, with or without eutectic alloys or adhesives layers, bumps with low temperature solders or direct bonding are extensively implemented techniques. 1-7 Moreover, for More Moore and More than Moore applications, low temperature bonding and metal bonding are becoming the main drivers of the latest developments. As copper is the main metal used for CMOS interconnects, a high-density Cu interconnection between layer structures, is expected for future three-dimensional integration of electronic devices fabricated on the basis of different technology/ design concepts. In this paper, an overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD and TEM analysis. Dedicated characterization techniques for such bonding are presented. Hybridization Techniques ReviewCopper is the most (compared to other possible bonding metals) promising candidate for 3D integration technology either for TSV filling or interstata hybridizing. The main reasons of this choice is the widely use of copper in semiconductor device industries and the cost of ownership. On the other hand, the choice of the metal bonding technique is still an open question. Bonding anneal temperature, duration of the annealing, need of an underfill, size and pitch of the interconnect pads, availability of the technique for wafer bonding or die bonding are key parameters of the final choice. The main studied bonding techniques can be divided into two groups: with and without thermal compression.Bonding with a compression force: Diffusion bonding.-The thermal compression bonding is a well known technique. 8-10 Wafers or dies are pressed together with a controlled force in a bonding tool, while heating is applied (400 C) to allow the bonding diffusion mechanism. Thanks to the compression force, the surfaces roughness is not a limiting factor as the surface asperities are deformed at the bonding interface, therefore surfaces with a roughness in the range of 5 nm can be used. Copper oxide should be avoided or removed right before ...

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A model of the defect formation at the bonding interface upon annealing in silicon wafer bonding is proposed in this paper. It is shown that the formation of the bonding defects depends on the thickness of the silicon oxide at the bonding interface. A mechanism of thermal voids formation is suggested based on the hydrogen solubility in amorphous silicon oxide. The interface gas quantity for various thicknesses of the buried oxide is predicted and good correlation with the experimental data is obtained.

The development of microcracks in hydrogen-implanted silicon has been studied up to the final split using optical microscopy and mass spectroscopy. It is shown that the amount of gas released when splitting the material is proportional to the surface area of microcracks. This observation is interpreted as a signature of a vertical collection of the available gas. The development of microcracks is modeled taking into account both diffusion and mechanical crack propagation. The model reproduces many experimental observations such as the dependence of split time upon temperature and implanted dose.

In this paper, SiGe nano-heteroepitaxy on Si and SiGe nano-pillars was investigated in a 300 mm industrial reduced pressure-chemical vapour deposition tool. An integration scheme based on diblock copolymer patterning was used to fabricate nanometre-sized templates for the epitaxy of Si and SiGe nano-pillars. Results showed highly selective and uniform processes for the epitaxial growth of Si and SiGe nano-pillars. 200 nm thick SiGe layers were grown on Si and SiGe nano-pillars and characterised by atomic force microscopy, x-ray diffraction and transmission electron microscopy. Smooth SiGe surfaces and full strain relaxation were obtained in the 650 °C-700 °C range for 2D SiGe layers grown either on Si or SiGe nano-pillars.