(Invited) Selective Epitaxial Growth (SEG) of Highly Doped Si:P on Source/Drain Areas of NMOS Devices Using Si₃H₈/PH₃/Cl₂ Chemistry

Abstract

In this paper we demonstrate the successful integration of in-situ doped Si:P epitaxially grown into the source/drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process employing a Si 3 H 8 /PH 3 /Cl 2 based chemistry. A distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We report on material characterization results of the Si:P selective epitaxial growth (SEG). An optimized Si:P SEG process with a SEG rate of ~25 nm/min enables a 80-170s short deposition for typical epitaxial layers (35-70 nm), well suitable for high volume manufacturing (HVM). By integrating an isothermal in-situ removal of Si 0.65 Ge 0.35 (protecting/covering the NMOS areas) with a high etch rate selectivity against the underlying thin SOI at process temperature allows to eliminate the in-situ H 2 prebake and the cool-down to process temperature, significantly reducing recipe overhead and the need for a separated, dedicated pre-clean module.

On the Evolution of Strain and Electrical Properties in As-Grown and Annealed Si:P Epitaxial Films for Source-Drain Stressor Applications

“…A monotonic increase in P concentration is observed similar to the reports from other groups. 8,10,11 An effect stemming from P incorporation is the development of lattice strain in Si:P films as shown in the (004) HR-XRD scans (Fig. 1b).…”

“…As P is an n-type dopant with a reduced covalent radius, Si:P films are expected to offer the combined advantages of better conductivity as well as tensile strain. [6][7][8][9] This motivation has led to a surge in the publications pertaining to the processing aspects of Si:P films 6,[8][9][10][11] and publications discussing the evolution of resistivities in the as grown and annealed Si:P films. 6,9,12 While the strain developed in the as-grown Si:P films increases with the total P concentration, the values of resistivity corresponding to those P concentrations were higher than the desired values for S/D applications i.e., higher than 0.3 mohm.cm.…”

Recrystallization and activation of ultra-high-dose phosphorus-implanted silicon using multi-pulse nanosecond laser annealing

“…5,6) An alternative approach for improving electron mobility in N-type MOSFETs is to use phosphorus-doped silicon for the source/drain. Highly phosphorus-doped silicon source/drain can impart a tensile strain [6][7][8][9][10] to the channel and consequently improve carrier mobility, whereas the source/drain resistivity of phosphorus doped silicon decreases as phosphorus concentration is increased. 6,[11][12][13] The conventional method for phosphorus doping is ion implantation; however, this can cause ion radiation damage (displacement of substrate atoms from their lattice sites) to the substrate.…”

Defect reduction and dopant activation of in situ phosphorus-doped silicon on a (111) silicon substrate using nanosecond laser annealing

“…n situ phosphorus-doped (ISPD) silicon has been actively investigated as a source/drain material to induce tensile strain in metal-oxide-semiconductor field-effect transistor (FETs) channels. [1][2][3][4][5][6] Here, the phosphorus atoms are incorporated into the silicon lattice, leading to a significant reduction in the lattice parameter of ISPD silicon 2,3) at the source/drain and consequent increase of the electron mobility by imposing the strain to the channels. 1,[6][7][8][9][10][11][12] Moreover, recent requirement of ultra-low contact resistivity pushes the employment of the high doping processes such as ISPD silicon epitaxial process by the phosphorous concentration at the source/drain up to 4 × 10 21 cm −3 .…”

“…[1][2][3][4][5][6] Here, the phosphorus atoms are incorporated into the silicon lattice, leading to a significant reduction in the lattice parameter of ISPD silicon 2,3) at the source/drain and consequent increase of the electron mobility by imposing the strain to the channels. 1,[6][7][8][9][10][11][12] Moreover, recent requirement of ultra-low contact resistivity pushes the employment of the high doping processes such as ISPD silicon epitaxial process by the phosphorous concentration at the source/drain up to 4 × 10 21 cm −3 . [13][14][15] This reduces the metal-semiconductor Schottky barrier width, which in turn increases the carrier tunneling and reduces the contact resistivity.…”