(Invited) Short Channel Effects and Drain Field Relief Architectures in Polysilicon TFTs

Abstract

Applications of polycrystalline silicon (polysilicon) thin film transistors (TFTs) to active matrix organic light emitting displays require further performance improvement. The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6μm to 1μm, or less. However, short channel effects and hot-carrier induced instability in scaled down conventional self-aligned polysilicon TFTs can substantially degrade the device characteristics. To reduce these effects and allow proper operation of the circuits, drain field relief architectures have to be introduced. In this work we show that a fully self-aligned gate overlapped lightly doped drain (LDD) structure, with submicron LDD regions, can provide an excellent solution, allowing effective short channel effect control and improved electrical stability.