(Invited) Water Stress Corrosion in Bonded Structures

Fournel, Frank; Martin-Cocher, Chloé; Radisson, Damien; Larrey, Vincent; Beche, Elodie; Morales, Christophe; Delean, P. A.; Rieutord, F.; Moriceau, H.

doi:10.1149/06405.0121ecst

Cited by 8 publications

(8 citation statements)

References 20 publications

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“…The dashed line with squares indicates bond strength measured using the razor blade test. 12 Since the bond strength reached nearly 5 J/m 2 , which is near the maximum that can be measured with the blade test, 13 the fracture often occurs within the Si wafer. This fracture in the Si bulk indicates that the LOR bonding interface and adhesion of LOR to Si surface is stronger than the Si bulk.…”

Section: Resultsmentioning

confidence: 94%

Temporary Bonding with Polydimethylglutarimide Based Lift Off Resist as a Layer Transfer Platform

Matsumae

Koehler

Greenlee

et al. 2015

ECS J. Solid State Sci. Technol.

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Bonding of lift off resist (LOR) was performed to realize temporary wafer bonding without residue. Bonding process conditions such as spin speed, pre-bake temperature, and bonding temperature were optimized to obtain a large bonded area with high bond strength. Under optimized process conditions, a bonded area covering over 98% of the wafer surface, with a room temperature bond strength of nearly 5 J/m 2 is achieved. During razor blade testing, fracture often occurs at the Si wafer. Moreover, debonding using an N-Methyl-2-pyrrolidone (NMP)-based solvent left the wafer surface extremely small amount of residue. Thus, the optimized bonding processed developed in this research is suitable for a clean temporary bonding process.

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Section: Resultsmentioning

confidence: 94%

Temporary Bonding with Polydimethylglutarimide Based Lift Off Resist as a Layer Transfer Platform

Matsumae

Koehler

Greenlee

et al. 2015

ECS J. Solid State Sci. Technol.

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“…Commonly, bonding energy is measured between two silicon wafers with thermal oxide by double cantilever beam (DCB) under prescribed displacement. As already described in literature [16], to avoid water stress corrosion effect, bonding energy has to be measured in an anhydrous atmosphere. In this case, process shift can more easily detected contrary to standard DCB method in cleanroom atmosphere.…”

Section: Low Temperature Bondingmentioning

confidence: 99%

(Invited) Hybrid Bonding for 3D Applications: Improvements and Limitations

Deloffre,

Ayoub,

Lhostis

et al. 2023

ECS Trans.

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With hybrid bonding pitch reduction, many challenges are arising such as optimized metrology measurement, bonding wave propagation understanding and hybrid surface characterization. By analyzing incoming wafer and how tool setting impacts bonding, overlay values below 110 nm for production wafers can be achieved with 100% electrical yield. Hybrid bonding extends further to IC Logic application or Memory and not only CMOS image sensor. For some of those products, the temperature of usual post bonding thermal annealing (400°C) cannot be applied. Consequently, many studies have been performed on developing low-temperature bonding. To add flexibility to hybrid bonding, new processes such as Surface Activation Bonding (SAB) and Die to Wafer bonding (D2W) have been developed to fit heterogenous integration.

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“…In addition, bonding benefits from pristine crystalline quality and accurate thickness control. It is important to highlight that even with a limited bonding anneal (<300°C), high energy bondings (4J<E bonding ) are achieved (22).…”

Section: Creation Of a Top Active Layermentioning

confidence: 99%

(Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration

et al. 2014

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By stacking transistor levels on each other sequentially, monolithic 3D integration appears to be an alternative solution to scaling. By taking fully advantages of the vertical dimension, circuit partitioning at the transistor scale is then possible. This paper reviews the different opportunities offered by such technology and summarizes the technological challenges related to this integration. A general overview of the different techniques to create an active layer above a bottom transistor level is presented. Direct bonding from a SOI wafer clearly appears to be currently the best solution to obtain a defect free monocrystalline active layer with a wellcontrolled thickness. Finally, the challenge of realizing a top transistor level with a low temperature thermal budget is explained. This thermal budget is quantified by studying the electrical stability of the bottom level. Some electrical results on low temperature activated junctions are also presented. M3D opportunities and design implicationsContrary to a parallel integration where wafers are processed separately and then connected -typically TSV-based 3D integrated circuits, monolithic 3D (M3D) consists in processing transistors sequentially on top of each other, as illustrated in Figure 1. Parallel integration (e.g: TSV ) Sequential integration σ //~1 000 nm σ SEQ~1 0nm Alignment performance Top layer thermal budget Limited Unlimitted 3D Contact process Challenging & costly planar scheme like 1/ Wafers separately processed 2/ Stacking and contacting 1/ Bottom transistor processing 2/ Top FET processing 3/ Contacting Figure 1. Comparison between parallel (TSV) and sequential (M3D) integration (1).ECS Transactions, 64 (5) 381-390 (2014) 381 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 129.82.28.124 Downloaded on 2015-06-28 to IP

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(Invited) Water Stress Corrosion in Bonded Structures

Cited by 8 publications

References 20 publications

Temporary Bonding with Polydimethylglutarimide Based Lift Off Resist as a Layer Transfer Platform

Temporary Bonding with Polydimethylglutarimide Based Lift Off Resist as a Layer Transfer Platform

(Invited) Hybrid Bonding for 3D Applications: Improvements and Limitations

(Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration

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