Ion beam synthesis of buried CoSi2-structures

Vogel, Tim; Meijer, Jan; Stephan, A.; Weidenmüller, U.; Dagkaldiran, Ü.; Kubsky, S.; Baving, P.; Becker, Hans‐Werner; Röcken, H.

doi:10.1016/s0168-583x(01)01070-9

Cited by 6 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Ion-beam nitrogen implantation is a flexible technique to create individual NV centers in a diamond sample [13,14] and two-qubit coupling was obtained between implanted nitrogen atoms coming from the dissociation of a nitrogen molecule impinging on a diamond surface [4,15]. However, the resolution of a nitrogen ion beam is limited to a few hundreds of nanometers even with ion optics correction [16], thus preventing the scale-up of this clever recipe. Alternative techniques enabling the reliable placement of nitrogen impurities into a diamond substrate have therefore to be developed.…”

Section: Introductionmentioning

confidence: 99%

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN⁻molecules through nanoapertures

et al. 2011

View full text Add to dashboard Cite

We report a versatile method to engineer arrays of nitrogen-vacancy (NV) color centers in diamond at the nanoscale. The defects were produced in parallel by ion implantation through 80 nm diameter apertures patterned using electron beam lithography in a PMMA layer deposited on a diamond surface. The implantation was performed with CN − molecules which increased the NV defect formation yield. This method could enable the realization of a solid-state coupled-spin array and could be used for positioning an optically active NV center on a photonic microstructure.

show abstract

Section: Introductionmentioning

confidence: 99%

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN⁻molecules through nanoapertures

et al. 2011

View full text Add to dashboard Cite

show abstract

“…Attempts have been taken by (i) using %100 keV Co ions irradiation at high fluence (%10 17 ions/cm 2 ) on Si followed by annealing at high temperature, a process known as ion beam synthesis [13][14][15][16]; (ii) using dual ion beam irradiations, i.e. %100 keV and %100 MeV ions irradiation at high fluence (%10 16 ions/cm 2 ) on thin film of Co on Si followed by annealing at high temperature [17][18][19][20]; and (iii) using focused ion beam [21,22]. In all the above-referred works, a thicker Co layer either through implantation or through physical deposition was used.…”

Section: Introductionmentioning

confidence: 99%

MeV Au ion induced modifications at Co/Si interface

Ghatak

Kabiraj

Satyam

2009

Applied Surface Science

View full text Add to dashboard Cite

“…[6][7][8] Most importantly, CoSi 2 is a promising candidate for addressing this R ext scaling issue because it is insensitive to the line width effect.…”

mentioning

confidence: 99%

“…[3][4][5] CoSi 2 has also been used for various Si-based applications such as buried CoSi 2 conducting patterns and a diffusion barrier and as a thermally stable metallization material for nanoparticles and nano-wires as well as compound semiconductors. [6][7][8] Most importantly, CoSi 2 is a promising candidate for addressing this R ext scaling issue because it is insensitive to the line width effect.…”

mentioning

confidence: 99%

Effect of CoSi₂Formation Process on CMOS Transistor Electrical Properties for Sub-100-nm Memory Applications

Park

Kim

Lee

et al. 2016

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

We investigated the effect of various processing conditions on abnormal CoSi 2 formation, such as the well-known Co spike and crystal agglomeration. We used Co metal sputtering and subsequent thermal treatment such as rapid thermal processing. The effect of the ion implantation conditions and Co deposition method were studied. To evaluate the electrical failure of transistors, we checked the chip level leakage current (I pp ), and the unit level leakage current (JLC) in the test pattern, simultaneously. As the dopant species and concentration were believed to affect the electrical properties of every single transistor, chip level leakage current and unit level leakage current deteriorate or improve simultaneously. When we used a Ti/TiN capping layer and high-temperature physical vapor deposition, abnormal growth was suppressed and the interface became smooth. The chip level leakage current in both cases showed significant improvement; however, the unit level leakage current showed a negligible change in contrast to the chip level one. We concluded that, despite no change in unit level leakage current, the overall level of chip level leakage current improved because of the significantly decreased number of defective sites such as Co spike. As complementary metal-oxide-semiconductor (CMOS) scaling occurs, the parasitic component of transistors, such as the external resistance (R ext ), plays an increasingly critical role in the overall electrical performance of transistors.1 Various components, which might be junctions, contacts, or metal interconnects, contribute to R ext . Most importantly, the contribution of R ext to degradation of metal contacts (the contact resistance) is the most serious problem, because the contact area decreases monotonously with feature size scaling of integrated circuits. Considering that the contact resistance is proportional to the resistivity ρ times the contact area A, we should reduce the resistivity significantly to meet the R ext requirement. However, the resistivity is also degraded with decreasing contact area owing to the well-known line width effect. 2The structural properties and formation behavior of cobalt silicide (CoSi 2 ) are of considerable practical interest for nano-electronic applications. Its high chemical inertness and thermal stability, together with its low resistivity, have promoted its use for metallization in integrated circuit fabrication.3-5 CoSi 2 has also been used for various Si-based applications such as buried CoSi 2 conducting patterns and a diffusion barrier and as a thermally stable metallization material for nanoparticles and nano-wires as well as compound semiconductors. [6][7][8] Most importantly, CoSi 2 is a promising candidate for addressing this R ext scaling issue because it is insensitive to the line width effect.It has been widely reported that the formation of cobalt silicide is directly affected by various surface states, such as the existence of silicon oxide and surface passivation.9-11 For this reason, extensive studies have been done ...

show abstract

Ion beam synthesis of buried CoSi2-structures

Cited by 6 publications

References 7 publications

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN⁻molecules through nanoapertures

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN⁻molecules through nanoapertures

MeV Au ion induced modifications at Co/Si interface

Effect of CoSi₂Formation Process on CMOS Transistor Electrical Properties for Sub-100-nm Memory Applications

Contact Info

Product

Resources

About

Ion beam synthesis of buried CoSi2-structures

Cited by 6 publications

References 7 publications

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN−molecules through nanoapertures

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN−molecules through nanoapertures

MeV Au ion induced modifications at Co/Si interface

Effect of CoSi2Formation Process on CMOS Transistor Electrical Properties for Sub-100-nm Memory Applications

Contact Info

Product

Resources

About

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN⁻molecules through nanoapertures

Engineered arrays of nitrogen-vacancy color centers in diamond based on implantation of CN⁻molecules through nanoapertures

Effect of CoSi₂Formation Process on CMOS Transistor Electrical Properties for Sub-100-nm Memory Applications