IP protection for VLSI designs via watermarking of routes

Narayan, N.; Newbould, Rexford D.; Carothers, J.D.; Rodriguez, J.J.; Holman, W.T.

doi:10.1109/asic.2001.954736

Cited by 30 publications

(20 citation statements)

References 6 publications

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“…[7]. At lower design levels, the approach was used even more effectively in routing [12], placement, and floor planning [9]. The main advantage of the approach is its real low overhead on the design cycle, as the NP-hard problem will be solved anyway.…”

Section: B Ip Watermarking: Related Workmentioning

confidence: 99%

Fragile IP Watermarking Techniques

Abdel-Hamid

Tahar

2008

2008 NASA/ESA Conference on Adaptive Hardware and Systems

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Abstract-Intellectual property (IP) blocks reuse is essential for facilitating the design process of system-on-a-chip. Sharing IP designs still poses significant high security risks not only to copyright but also to design authenticity. Intruders, or even competitors, can make design changes to IPs, which can lead to the loss of the owner's credibility. In this paper, we are trying to solve such challenge by proposing a novel fragile IP watermarking technique. The proposed technique protects hardware designs from alteration or any modifications that might occur to the design. The approach utilizes existing transitions in a finite state machine (FSM) component of an IP and does not result on any overhead to the IP design. Finally, we implemented the algorithm proposed and tested it.

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Section: B Ip Watermarking: Related Workmentioning

confidence: 99%

Fragile IP Watermarking Techniques

Abdel-Hamid

Tahar

2008

2008 NASA/ESA Conference on Adaptive Hardware and Systems

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“…Then, the scheme adds the constraints into the original design specification, with the help of a tool that retrieves the final optimized design specification. Narayan et al [12] proposed a process for embedding a watermark by modifying the number of vias or bends utilized to route the nets in a design. All these techniques embed the watermark at the physical design stage [10], [13]- [16], design partitioning [17], [18], and combinational logic synthesis [15].…”

Section: Introductionmentioning

confidence: 99%

An AES-based Intellectual-Property Identification in System-on-a-Chip Design

Gopinath¹,

Adithya²,

Ajay³

2013

IJCA

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This paper presents a novel intellectual-property (IP) identification scheme using the existing System-on-aChip (SOC) watermarking design. An efficient and novel principle is established for IP identification which depends on the current IP design flow. The principle is embedding different Advanced Encryption Standard (AES) encoders in to System-on-a-Chip (SOC) based watermarked devices at behavior design level. Here the AES encoders provide additional security to the previously generated watermark sequences. This method is efficient as it survives synthesis, placement, and routing and can identify the IP at various levels. It may be easy to detect the identification of the provider even after the chip has been manufactured. The proposed method increases security for the System-on-a-Chip (SOC) based IP identification and protection scheme. KeywordsIntellectual-Property (IP) identification, system-on-achip (SOC), very large scale integration (VLSI) design, watermarking, Advanced Encryption Standard (AES).

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“…In the other scheme, they attacked the FPGA watermarking proposed by Lach et al [24], where they located the embedded signature and then removed it. The authors though, did not try to attack this approach at lower levels such as placement [19] or routing [27]. We believe deleting the watermark at these levels is much harder.…”

Section: Static Watermarking Techniques: Constraint-based Ip Watermarmentioning

confidence: 99%

“…At the system level, for instance, it was used to watermark memory graph coloring problems [14], as well as graph partitioning problems [46] and linear programming problems [26]. At lower design levels, the approach was used even more heavily with routing [27], placement, and floor planning [19]. In [32], Qu developed the first public watermarking approach based on the above technique.…”

Section: Static Watermarking Techniques: Constraint-based Ip Watermarmentioning

confidence: 99%

A Survey on IP Watermarking Techniques

Abdel-Hamid

Tahar

Aboulhamid

2004

Des Autom Embed Syst

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Abstract. Intellectual property (IP) block reuse is essential for facilitating the design process of system-ona-chip. Sharing IP designs poses significant high security risks. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, we survey and classify different techniques used for watermarking IP designs. To this end, we defined several evaluation criteria, which can also be used as a benchmark for new IP watermarking developments. Furthermore, we established a comprehensive set of requirements for future IP watermarking techniques.

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IP protection for VLSI designs via watermarking of routes

Cited by 30 publications

References 6 publications

Fragile IP Watermarking Techniques

Fragile IP Watermarking Techniques

An AES-based Intellectual-Property Identification in System-on-a-Chip Design

A Survey on IP Watermarking Techniques

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