Island-edge effects in C-MOS/SOS transistors

Lee, S.N.; Kjar, R. A.; Kinoshita, G.

doi:10.1109/t-ed.1978.19209

Cited by 28 publications

(6 citation statements)

References 7 publications

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“…More recent studies on SOS island edge effects have been carried out by Lee and Kjar 156,157 and Maeguchi et ai. 158 Their results also indicate that island edge effects can be minimized by proper process selection.…”

Section: A Leakage Currentsmentioning

confidence: 99%

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The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

Ipri

1981

Silicon Integrated Circuits

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Section: A Leakage Currentsmentioning

confidence: 99%

“…177 Devices which exhibit the characteristics shown in Fig. 157 Lee and Kjar 157 used a scanning electron microscope (SEM) to examine the edges of SOS-MOS structures with relatively thick oxides and found that a V-shaped groove can form between the oxidized silicon film and the sapphire surface as shown in Fig. 59.…”

Section: Other Anomalous Effectsmentioning

confidence: 99%

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

Ipri

1981

Silicon Integrated Circuits

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“…At Ϫ1 V, the leakage current through the gate stack is more than four orders smaller than the anticipated current in SiO 2 film with the same EOT. 15 From Fig. 2, it is evident that the leakage current shows a different temperature dependence in different field regions.…”

Section: Resultsmentioning

confidence: 94%

Electrical Properties of Al[sub 2]O[sub 3]/ZrO[sub 2]/Al[sub 2]O[sub 3] Gate Stack in p-Substrate Metal Oxide Semiconductor Devices

Kaczer

Degraeve

et al. 2003

J. Electrochem. Soc.

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The electrical properties of the Al 2 O 3 /ZrO 2 /Al 2 O 3 gate dielectric stack are investigated in p-substrate metal oxide semiconductor capacitors and transistors. It is found that the leakage current through the gate stack shows different temperature dependence in low-and high-field regions. This is explained by the different conduction mechanisms at the low and high gate bias. The leakage current is mainly due to tunneling in the low field region, while both tunneling and Frenckel-Poole hopping are involved in the conduction in the high-field region. After constant current stress, both increase of leakage current and positive charge generation are observed. It is also found that the breakdown always occurs in the source/drain overlapped region after uniform voltage stress of the gate stack. The weaker overlapped region is related to ion implantation-induced crystal defects or high doping concentration in the source/drain regions.

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“…63 In SOI devices a new phenomenon has recently been reported, i.e., the linear kink effect, 37,66 where for a sufficiently high gate bias, a substrate current can be injected by direct tunneling across the ultrathin gate oxide. 67 For an n-MOSFET, electron valence band ͑EVB͒ tunneling creates holes in the valence band, which flow to the substrate contact or charge the body of a floating-body SOI transistor. [66][67][68] Similarly to the impact-ionization related kink effect, this generates a kink in the drain current.…”

Section: Impact Of the Silicon Substrate Parameters On The Lf Noisementioning

confidence: 99%

Low-Frequency Noise Assessment for Deep Submicrometer CMOS Technology Nodes

Claeys

Mercha

Simoen

2004

J. Electrochem. Soc.

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This overview focuses on the different types of noise occurring in deep submicrometer silicon metal oxide semiconductor field-effect transistors and their use as an analytical tool. The noise sources comprise white noise, generation-recombination noise, random telegraph signal fluctuations, and 1/f or flicker noise. The fundamental basis of each noise type is briefly described and illustrated by some practical examples. In a second part, the impact of the properties of the silicon substrate (orientation, crystallization technique, silicon-on-insulator, SiGe) on the noise performance is discussed. Finally, the influence on the low-frequency noise behavior of different advanced process modules, such as gate stack, device isolation, silicidation, and gate engineering, is illustrated. © 2004 The Electrochemical Society. All rights reserved.

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Island-edge effects in C-MOS/SOS transistors

Cited by 28 publications

References 7 publications

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

The Properties of Silicon-on-Sapphire Substrates, Devices, and Integrated Circuits

Electrical Properties of Al[sub 2]O[sub 3]/ZrO[sub 2]/Al[sub 2]O[sub 3] Gate Stack in p-Substrate Metal Oxide Semiconductor Devices

Low-Frequency Noise Assessment for Deep Submicrometer CMOS Technology Nodes

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