Isochronous data link across a superconducting Nb flex cable with 5 femtojoules per bit^*

Abstract

Interconnect properties position superconducting digital circuits to build large, high performance, power efficient digital systems. We report a board-to-board communication data link, which is a critical technological component that has not yet been addressed. Synchronous communication on chip and between chips mounted on a common board is enabled by the superconducting resonant clock/power network for Reciprocal Quantum Logic circuits. The data link is extended to board-to-board communication using isochronous communication, where there is a common frequency between boards but the relative phase is unknown. Our link uses over-sampling and configurable delay at the receiver to synchronize to the local clock phase. A single-bit isochronous data link has been demonstrated on- chip through a transmission line, and on a multi-chip module through a superconducting tape between driver and receiver with variable phase offset. Measured results demonstrated correct functionality with a clock margin of 3 dB at 3.6 GHz, and with 5 fJ/bit at 4.2 K.

Extremely large area (88 mm × 88 mm) superconducting integrated circuit (ELASIC)

“…Additionally, increasing the integration scale through packaging is a larger driver of SCE, for which on-carrier memory offers a significant benefit. By adding an active junction layer within the carrier, this approach favors active-to-active bonding with short distances between active elements such as logic and memory (see Supplemental Materials S1), enabling higher bandwidth and lower latency communications than an equivalent active-to-passive platform 28 , 29 .…”

“… Junction devices were integrated into the passive chip carrier to increase functionality (i.e., active transmission lines, drivers, receivers, repeaters, transformers, amplifiers, etc.). Reduced feature size (2.2X smaller line width than passive chip carrier 28 , 29 ) Reduce via diameter (6X smaller than passive chip carrier 28 , 29 ) Smaller resistor (2X smaller resistor width and via diameter than passive chip carrier 28 , 29 ) Use deep UV lithography for microbump fabrication (see Supplemental Materials S1) with reduced micro-bump pitch (2X–12X smaller micro-bump pitch than passive chip carrier 30 – 32 ) …”

Disentangling superconductor and dielectric microwave losses in sub-micron $\rm Nb$/$\rm TEOS-SiO_2$ interconnects using a multi-mode microstrip resonator

“…Measurements were taken at 4.2K in a LHe Dewar using an RF dip probe equipped with a 32-contact-pad test fixture. 11,18,19,21 To provide for fast sample exchange, a flip-chip press-contact technology is used, where the chip contact pads are pressed against the fixture non-magnetic Cu/Au bumps. The fixture PCB interfaces the bumps to the probe semi-rigid coaxial cables.…”

“…On one hand, they can provide a basic building block for GHz clock and power distribution systems. 11,18,19 On the other hand, they can form a passive transmission line, to propagate low-bandwidth (35-50 GHz) data with 7-10 SFQ pulses per bit, 19 or to propagate high-bandwidth (350 GHz) data with single SFQ pulse per bit, 20,21 or to produce a delay-line memory. 22 The power dissipation is governed by the superconductor and dielectric loss, and is inversely proportional to a transmission line resonator figure of merit, quality factor (Q-factor).…”

Synchronous chip-to-chip communication with a multi-chip resonator clock distribution network *

“…Synchronous communication can be used in systems where the fabrication-related skew between wires is small relative to the timing window of the receiver, about one phase of the RQL clock. For larger systems involving board-to-board communication isochronous protocol is required, as described in [25].…”