Issues and Support for Dynamic Register Allocation

Das, Abhinav; Fu, Rao; Zhai, Antonia; Hsu, Wei-Chung

doi:10.1007/11859802_29

Cited by 2 publications

(1 citation statement)

References 9 publications

(3 reference statements)

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“…As it is shown in [7], dynamic register allocation is a problem that needs to be addressed when implementing a dynamic optimizer. Register allocation on the Itanium processor is achieved using the alloc instruction.…”

Section: Register Usagementioning

confidence: 99%

Performance driven data cache prefetching in a dynamic software optimization system

Beyler¹,

Clauss²

2007

Proceedings of the 21st Annual International Conference on Supercomputing

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Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximize their positive impact while minimizing their negative impact on performance. In previous proposed dynamic frameworks, the monitoring scheme is either achieved using processor performance counters or using specific hardware. In this work, we propose a prefetching strategy which does not use any specific hardware component or processor performance counter. Our dynamic framework wants to be portable on any modern processor architecture providing at least a prefetch instruction. Opportunity and effectiveness of prefetching loads is simply guided by the time spent to effectively obtain the data. Every load of a program is monitored periodically and can be either associated to a dynamically inserted prefetch instruction or not. It can be associated to a prefetch instruction at some disjoint periods of the whole program run as soon as it is efficient. Our framework has been implemented for Itanium-2 machines. It involves several dynamic instrumentations of the binary code whose overhead is limited to only 4% on average. On a large set of benchmarks, our system is able to speed up some programs by 2%-143%.

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Section: Register Usagementioning

confidence: 99%

Performance driven data cache prefetching in a dynamic software optimization system

Beyler¹,

Clauss²

2007

Proceedings of the 21st Annual International Conference on Supercomputing

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Issues and Support for Dynamic Register Allocation

Das

Zhai

et al. 2006

Advances in Computer Systems Architecture

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Post-link and dynamic optimizations have become important to achieve program performance. This is because, it is difficult to produce a single binary that fits all micro-architectures and provides good performance for all inputs. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code with the main program. We show that it is difficult to achieve both correctness and transparency when only software schemes for acquiring registers are used. We then propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. The hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a "safe" manner, thus preserving the transparency and improving the performance of these systems.

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Issues and Support for Dynamic Register Allocation

Cited by 2 publications

References 9 publications

Performance driven data cache prefetching in a dynamic software optimization system

Performance driven data cache prefetching in a dynamic software optimization system

Issues and Support for Dynamic Register Allocation

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