Issues in embedded DRAM development and applications

Keitel-Schulz, D.; Wehn, N.

doi:10.1109/isss.1998.730592

Cited by 7 publications

(1 citation statement)

References 9 publications

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“…This concept became popular around 1997 in COM-N architectures and was further developed until 2002. These COM-N architectures, such as VIRAM [69] (initially named IRAM), DIVA [24] or FlexRAM [62], never commercialized due to the limitations of embedded DRAM technology (i.e., costly fabrication process, and inefficient speed and memory capacity trade-off [54,63,64]). After that, a long silent period in academia community was observed from 2002 to 2010.…”

Section: Classificationmentioning

confidence: 99%

A Classification of Memory-Centric Computing

Nguyen

Lebdeh

et al. 2020

J. Emerg. Technol. Comput. Syst.

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Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures; it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.

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