Issues on the size and outline of killer defects and their influence on yield modeling

Hess, Christopher P.; Weiland, L.H.

doi:10.1109/asmc.1996.558102

Cited by 13 publications

(7 citation statements)

References 12 publications

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“…16-18 also contain layer-specific size distributions based on optical measurements using a technique called Micro Size Distribution (MSD). It was introduced by [12] and is also described in Appendix A. We included two curves per Figure, each based on the same set of optical data but distributed among differently sized intervals.…”

Section: Resultsmentioning

confidence: 99%

“…Each imaginary defect has to be weighted with because all w imaginary defects represent just one original defect. So, the absolute occurrence of detected defects remains unchanged, if and only if for each defect (12) where is the total number of size intervals and stands for the number of imaginary defects per size interval. For example, the defect of Fig.…”

Section: Appendix a Micro Size Distribution (Msd)mentioning

confidence: 98%

“…Based on these values, a defect size distribution will be determined. To also include the irregular outlines of defects that occur in reality, we introduced a general defect size distribution based on individual size distributions for each detected defect [12].…”

Section: Appendix a Micro Size Distribution (Msd)mentioning

confidence: 99%

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Harp test structure to electrically determine size distributions of killer defects

Hess¹,

Weiland²

1998

IEEE Trans. Semicond. Manufact.

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To improve accuracy of electrically based measurements of defect densities and defect size distributions, we present a novel Harp Test Structure (HTS). There, horizontal and vertical parallel lines will be placed inside a given boundary pad frame without using any additional active semiconductor devices. The enhanced two-dimensional (2D) permutation sequence provides that all neighborhood relationships of adjacent test structure lines are unique. This is the key to disentangle even multiple faults detected by fast digital measurements. For this reason, the number and size of individual defects will be extracted anywhere inside or in-between layers. Experimental results show, that not only optical measurements, but also electrical measurements at a Harp Test Structure are sufficient to get a precise defect size distribution that enables size distribution modeling for yield prediction.

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Section: Resultsmentioning

confidence: 99%

Section: Appendix a Micro Size Distribution (Msd)mentioning

confidence: 98%

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Harp test structure to electrically determine size distributions of killer defects

Hess¹,

Weiland²

1998

IEEE Trans. Semicond. Manufact.

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“…The modeling of real defect outlines that exhibit a great variety of defect shapes is usually modeled as circular available [4][5][6]. Hess and Weiland [7] pointed out that the outlines of defects can be classified into three types: type-0, type-1, and type-2, and of all the inspected defects yields, 23% are type-0 defects, 67% are type-1 defects, and just 10% are type-2 defects. Our investigation results show that 25.73% of all the inspected defects belong to type-0, 50.88% to type-1, and 23.39% to type-2.…”

Section: Introductionmentioning

confidence: 99%

Yield modeling of elliptical defect

Wang

Zhuo-kui

Chunli

et al. 2007

Front. Electr. Electron. Eng. China

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Physical defects have always played an important role in integrated circuit (IC) yields, and the design sensitivity to these physical elements has continued to increase in today's nanometer technologies. The modeling of defect outlines that exhibit a great variety of defect shapes is usually modeled as a circle, which causes the errors of critical area estimation. Since the outlines of 70% defects approximate to elliptical shapes, a novel yield model associated with elliptical outlines of defects is presented. This model is more general than the circular defects model as the latter is only an instance of the proposed model. Comparisons of the new and circular models in the experiment show that the new model can predict yield caused by real defects more accurately than what the circular model does, which is of significance for the prediction and improvement of the yield.

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“…The modeling of real defect outlines that exhibit a great variety of defect shapes is usually modeled as a circle, which causes error of critical area simulation [6][7][8]. Various new models have been experimented which can predict real defects in a much better way than the usual circular model does [9,10]. Activities for improving yield and quality by applying various analyses are conducted routinely.…”

Section: Introductionmentioning

confidence: 99%

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

Oberai

Yuan

2018

Electronics

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With the increase in the complexity of the semiconductor device processes and increase in the challenge to satisfy high market demands, enhancement in yield has become a crucial factor. Discovering and reacting to yield problems emerging at the end of the production line may cause unbearable yield loss leading to larger times to market. Thus, time and cost involved in fault isolation may be significantly shortened by effectively utilizing the fault diagnosis technology and supporting yield improvements. Hence for yield analysis, a highly integrated data network with software analysis tools have been established to reduce the fault analysis time. Synopsys Avalon, a product used for fault localization is described in this paper which aids in achieving better integrated circuit yields. This paper also illustrates various fault localization techniques for faster problem identification and discusses a few analytical tools like photon emission microscope and transmission emission microscope for faster determination of device failures.

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Issues on the size and outline of killer defects and their influence on yield modeling

Cited by 13 publications

References 12 publications

Harp test structure to electrically determine size distributions of killer defects

Harp test structure to electrically determine size distributions of killer defects

Yield modeling of elliptical defect

Efficient Fault Localization and Failure Analysis Techniques for Improving IC Yield

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