Iterative placement improvement by network flow methods

Abstract

We describe an efficient iterative improvement procedure for row-based cell placement with special emphasis on the objective function used to model net lengths. Two new net models are introduced and we prove theoretically that the net models are accurate approximations of the widely used half perimeter of a rectangle enclosing all pins of a net. In addition, unlike the half perimeter model, our net models allow us to compute costs for assigning cells to locations independently for all cells to be placed simultaneously. This offers our algorithm an important advantage compared to other iterative improvement techniques: many cells can be placed simultaneously by formulating placement as a network flow problem. This makes our algorithm more independent from a processing sequence than standard iterative improvement techniques. Finally, we compare our method to some existing algorithms including TimberWoifSC 5.4. We ran all of the algorithms on the SIGDA Benchmark Suite. We found that our method produced solutions with up to 23% less layout area while using an order of magnitude less running time compared to TimberWolfSC 5.4.

A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs

“…Table 3 shows that even starting with circuits placed by a TD placer, we can improve results appreciably-with 10% WS, we get up to about 10% and an average of 6.17% delay improvement. 5 All placement results reported here including that of FlowPlace are without row spacing, as is also the case for results in [14,15]. FlowPlace's delay improvements with row spacing are a little better (by 2-4.5%) than without row spacing; see [7].…”

“…3(a) shows a generic network flow graph with arc costs and capacities, and a minimum cost flow of some amount x from the source node S to the sink node T that passes through the network. Network flow has found application in VLSI CAD problems ranging from partitioning to placement [4,5,16].…”

“…The detailed placement algorithm uses a network flow based method. Network flow has been used previously for solving the legalization problem in standard-cell circuits [4,5]. In both works, the network flow modeling is similar to ours on some high-level issues: cells are represented by nodes and possible movement of cells are represented by arcs from them to destination positions.…”

FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model

“…In our experiments we have compared FastPlace with state-ofthe-art academic placers -Capo 8.8 [16], Dragon 2.2.3 [15] and Gordian-Domino [10], [31].…”

On-Line Adjustable Buffering for Runtime Power Reduction

“…Detailed placement is a refinement step which performs small-range perturbations to generate a new optimized placement. Several approaches to detailed placement have been proposed with most focusing on wirelength minimization (e.g., [6]) or timing [5]. Our approach, to the best of our knowledge, is the first to consider the impact of detailed placement on poly gate pitch to reduce leakage which is strongly and systematically dependent on pitch.…”