This paper focuses on real-time pedestrian detection onField Programmable Gate Arrays (FPGAs) using the Histograms of Oriented Gradients (HOG) descriptor in combination with a Support Vector Machine (SVM) for classification as a basic method. We propose to process image data at twice the pixel frequency and to normalize blocks with the L1-Sqrt-norm resulting in an efficient resource utilization. This implementation allows for parallel computation of different scales. Combined with a time-multiplex approach we increase multiscale capabilities beyond resource limitations. We are able to process 64 high resolution images (1920 × 1080 pixels) per second at 18 scales with a latency of less than 150 μs. 1.79 million HOG descriptors and their SVM classifications can be calculated per second and per scale, which outperforms current FPGA implementations by a factor of 4.

A new partitioning approach for very large circuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that prots from a linear objective function, signicantly improves the partitioning quality compared to the well-known eigenvector approach, which minimizes a quadratic objective function. For the rst time, results of benchmark circuits with up to 100,000 cells are presented. The cutsize and the minimum ratio cut is improved up to 90%. The average improvement is about 50%.

We describe an efficient iterative improvement procedure for row-based cell placement with special emphasis on the objective function used to model net lengths. Two new net models are introduced and we prove theoretically that the net models are accurate approximations of the widely used half perimeter of a rectangle enclosing all pins of a net. In addition, unlike the half perimeter model, our net models allow us to compute costs for assigning cells to locations independently for all cells to be placed simultaneously. This offers our algorithm an important advantage compared to other iterative improvement techniques: many cells can be placed simultaneously by formulating placement as a network flow problem. This makes our algorithm more independent from a processing sequence than standard iterative improvement techniques. Finally, we compare our method to some existing algorithms including TimberWoifSC 5.4. We ran all of the algorithms on the SIGDA Benchmark Suite. We found that our method produced solutions with up to 23% less layout area while using an order of magnitude less running time compared to TimberWolfSC 5.4.

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