ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET

Mathew, L.; Sadd, M.; Kalpat, S.; Zavala, M.; Stephens, T.; Mora, R.; Rai, R.; Parker, Courtney; Vasek, Jim; Sing, David C.; Shinier, R.; Prabhu, L.; Workman, G.O.; Ablen, G.; Shi, Zaifeng; Saenz, Javier; Min, Byung-Jun; Burnett, D.; Nguyen, Bich‐Yen; Mogab, J.; Chowdhury, M.M.; Zhang, W.; Fossum, J.G.

doi:10.1109/icicdt.2006.220809

Cited by 3 publications

(5 citation statements)

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“…Functional SRAM bitcells have been demonstrated using ITFET [16 ]. In general, ITFET devices are very useful in circuits that need ratioing such as in SRAM cells.…”

Section: Fig 10 Shows the Implementation Of A Migfet Transistor Withmentioning

confidence: 99%

“…The Delta device morphed subsequently into a FinFET transistor [13] defined on an SOI substrate which, along with process simplification, provides the added advantage of full isolation of the transistor from the rest of the wafer. In the meantime the FinFET transistor spawned a numerous progeny of novel devices such as Tri-gate transistor [14], MIGFET [15], ITFET [16], Multi-channel FinFET (MC-FinFET) [17], Multi-Bridge-Channel (MBCFET) [18], and Multi-Channel FET (McFET) [19] FinFET-based transistors. The discussion of these transistors is the object of the subsequent section.…”

Section: Fig5 Vertical Gate Replacement Transistor [11]mentioning

confidence: 99%

“…One recent example of such innovation is the ITFET (for Inverted T Channel-Field Effect Transistor) [16 ], a close cousin of a FinFET transistor. This device, features a combination of vertical and planar thin body structures within a single transistor and offers some advantages over the FinFET.…”

Section: Ecsmentioning

confidence: 99%

“…On the other hand, by virtue of its greater flexibility of defining the effective width, the ITFET offers an elegant solution for designing an optimized SRAM bitcell. Functional SRAM bitcells have been demonstrated using ITFET [16 ]. In general, ITFET devices are very useful in circuits that need ratioing such as in SRAM cells.…”

Section: Ecsmentioning

confidence: 99%

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Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?

Orłowski¹,

Wild²

2006

ECS Trans.

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Beyond 2007, when the channel length is projected to be 25 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 25 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge. Non-classical double-gate, ultrathin-body transistors offer to minimize short-channel effects and allow for more aggressive scaling. Several three-dimensional (3-D) multigate structures such as FinFET, Trigate, MIGFET, ITFET have been demonstrated with good electrical characteristics down to gate lengths of 10 nm. The manufacturing of 3D devices is entirely compatible with the integration processes employed for planar CMOS MOSFETs. Provided that fabrication, yield, design, and cost issues can be rendered tractable, 3D devices are poised to breathe new life into Moore's Law and close the gap between traditional CMOS planar MOSFETs and post-CMOS-era starting at gate lengths of 6 nm. Introduction: The Driving Forces for Transistor ScalingThe 2005 revision of the International Technology Roadmap for Semiconductor Industry [1] is showing a change in technology node introduction from a two-year to a three-year cycle. A stable rate of about 30% of transistor scaling every two years, observed over the last four decades, is about to slow down to about 30% decrease of transistor size every three years. (The technology nodes are, most commonly, specified by the minimum half-pitch of first metal interconnect.) This is not the first time that the technology roadmap predicts a slow down in transistor scaling: the very first edition of ITRS (TRS in 1994) prognosticated that the technology nodes beyond half-micron, i.e. starting with 0.35µm, will require three years to be developed and deployed. The past decade appears to teach that such forecasts have been received by the industry as targets to be exceeded. The 90 nm node went into production in 2003, 65 nm node is being currently introduced into production, and 45 nm technology is expected -as per ITRS roadmap -to be in production sometime during 2009-2010. However, many IDMs are striving to achieve this milestone a year or more earlier than forecasted by ITRS. Many of the front-end and back-end process challenges relate to the realization that continued CMOS scaling will require the introduction of new materials, new processes, and new transistor architectures in order to perpetuate Moore's Law [2] for the foreseeable future. Various responses to the crucial challenge of CMOS scaling seek to reconcile the conflicting requirements of reducing the transistor area, reducing the dynamic power, and reducing off-state power consumption, while increasing the circuit performance. At the present point in time, continued transistor scaling is causing currently used front-end materials to approach their fundamental physical limits. The most prominent example is the disappearing gate silicon dioxide approaching a physical thickness of two atomic layers. The limited ability of photolithography to produce small features i...

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“…Functional SRAM bitcells have been demonstrated using ITFET [16 ]. In general, ITFET devices are very useful in circuits that need ratioing such as in SRAM cells.…”

Section: Fig 10 Shows the Implementation Of A Migfet Transistor Withmentioning

confidence: 99%

Section: Fig5 Vertical Gate Replacement Transistor [11]mentioning

confidence: 99%

Section: Ecsmentioning

confidence: 99%

Section: Ecsmentioning

confidence: 99%

See 2 more Smart Citations

Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?

Orłowski¹,

Wild²

2006

ECS Trans.

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show abstract

“…This can be alleviated by an extremely tight pitch control, increasing the process complexity and statistical CD variation. [7][8][9][10][11][12][13] To provide an alternate perspective, we report a wavy continuous channel FinFET-like transistor that combines a 2D UTB planar and a 3D fin non-planar architecture of device on an SOI platform. Through simulations and experimental results, we show that compared to conventional FinFETs, the wavy channel transistor is capable of providing an enhanced drive current capability while consuming a lower chip area and providing a relaxed fin-fin pitch.…”

mentioning

confidence: 99%

Wavy channel transistor for area efficient high performance operation

Fahad

Hussain

Sevilla

et al. 2013

Applied Physics Letters

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We report a wavy channel FinFET like transistor where the channel is wavy to increase its width without any area penalty and thereby increasing its drive current. Through simulation and experiments, we show the effectiveness of such device architecture is capable of high performance operation compared to conventional FinFETs with comparatively higher area efficiency and lower chip latency as well as lower power consumption.

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Effect of Temperature on RF and Linearity Performance of Inverted-T FinFET

Gulhane,

Mishra

2024

Trans. Electr. Electron. Mater.

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ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET

Cited by 3 publications

References 0 publications

Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?

Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?

Wavy channel transistor for area efficient high performance operation

Effect of Temperature on RF and Linearity Performance of Inverted-T FinFET

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