Wavy channel transistor for area efficient high performance operation

Abstract

We report a wavy channel FinFET like transistor where the channel is wavy to increase its width without any area penalty and thereby increasing its drive current. Through simulation and experiments, we show the effectiveness of such device architecture is capable of high performance operation compared to conventional FinFETs with comparatively higher area efficiency and lower chip latency as well as lower power consumption.

Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application

“…HP applications mainly target to achieve high current drivability as well as density instead of thinking about the off state leakage current. Hence, to achieve the HP computing operation, a novel hybrid transistor i.e., ITFET [7e9] was first proposed by Mathew et al and Zhang et al The device is further explored by Fahad et al [4,10] in order to optimize the UTB layer and they have renamed as Wavy FinFET. Wavy FinFET merges two different and emerging technologies in the same SOI platform, i.e., 2-D UTB MOSFET and 3-D FinFET [11,12].…”

Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

“…Therefore, a fin type feature vertically integrated wavy channel (WC) architecture can play critical role to increase the width, in the direction perpendicular to the substrate, without increasing the transistor area. We have previously shown the usefulness of this new architecture both for logic transistors and for polysilicon TFTs 5, 6. This novel architecture is shown in Fig.…”

3-D TCAD Assessment of Fin-Based Hybrid Devices Under Heavy Ion Irradiation in 20-nm Technology

“…Out of these research efforts, the hybrid FinFETs are of great interest that was initially proposed by M athew et al [8] and Zhang et al [9] as an inverted-T FET. Hybrid FinFETs merge several technologies in a single SOI platform namely three dimensional (3-D) FinFET and two dimensional (2-D) ultra-thin body (UTB) MOSFET as reported by F ahad et al [10], [11]. In order to analyze the impact of high-k spacer technology in the hybrid FinFETs, P radhan et al [12]- [14] have quantitatively explored the effect of high-k spacer length on various performance matrix of the hybrid devices.…”