Junction optimization for Reliability issues in floating gate NAND flash cells

Lee, C. H.; Yang, I-Chen; Lee, Chienying; Cheng, C.H.; Chong, L. H.; Chen, K. F.; Huang, Jen-Wei; Ku, S.H.; Zous, N.K.; Huang, I. J.; Han, T. T.; Chen, M. S.; Lü, Wei; Chen, K. C.; Wang, Tahui; Lu, Chih‐Yuan

doi:10.1109/irps.2011.5784549

Cited by 8 publications

(3 citation statements)

References 14 publications

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“…The performance of the memory cells is determined by the programming speed, which is dominated by the speed of the erasing and writing operations [ 1 , 2 ]. The speed is basically limited by the rate at which electrons can be pumped into (writing) and out of (erasing) the devices without causing damage to the device [ 1 , 5 , 6 , 7 ]. Typically, writing and erasing operations must be capable of operating within 1 ms at a specified applied voltage [ 1 , 6 , 8 , 9 , 10 , 11 ].…”

Section: Introductionmentioning

confidence: 99%

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

et al. 2022

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To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

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Section: Introductionmentioning

confidence: 99%

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

et al. 2022

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“…Different values were found in NOR arrays, owing once more to differences in cell design and cycling conditions. Such dependences prompted several works and studies on the optimization of the cell process/architecture in order to reduce the extent of the RTN [124,[126][127][128][129][130][131][132][133][134]. In the NAND array, moreover, the RTN amplitude was shown to depend on the cell position and state along the string [135,136] (because of the different transconductances, depending on the source and drain series resistances) and on the state of cells on adjacent BLs [137] (because of the modification in the electron density profile induced by electrostatic interference).…”

Section: Main Experimental Datamentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…It is well known that omit to avoid program disturbance, the scaled cell gate length cannot increase the boron channel doping concentration. Correspondingly, the S/D doping must be reduced to suppress short channel effect (SCE) and program disturbance, [18][19][20][21][22] thus warranting a more thorough investigation of RTN for the cell with low or eliminated S/D doping levels. Even without S/D doping, fringing fields induced by neighboring floating gates (FGs) can produce an adequate number of surface electrons and achieve a sufficient string ON-current level.…”

Section: Introductionmentioning

confidence: 99%

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

Li¹,

Shirota²

2013

Jpn. J. Appl. Phys.

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A comprehensive numerical study of threshold voltage fluctuation (ΔV T) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of ΔV T is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (V pass) and the neighboring cell V T (V T(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, ΔV T increases in the S/D region as V pass - V T(n) decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high ΔV T area moves from the AA edge towards the center area along the W-direction.

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Junction optimization for Reliability issues in floating gate NAND flash cells

Cited by 8 publications

References 14 publications

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

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