Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application

Lin, Jer-Yi; Kuo, Po-Yi; Lin, Ko-Li; Chin, Chun-Chieh; Chao, Tien−Sheng

doi:10.1109/ted.2016.2615805

Cited by 18 publications

(5 citation statements)

References 19 publications

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“…However, there are more negative V TH and worse subthreshold characteristics in JL devices with thicker thickness of channel (a-IWO channel = 10 nm) or under poorer gate controls (HfO 2 GI = 30 nm for BMG and SiO 2 GI = 30 nm for BSG) in Fig. 2 21 . Among these devices, the transfer characteristics of BSG a-IWO NS-JLTs with a-IWO channel = 4 nm and SiO 2 GI = 30 nm exhibit the weakest gate control on channel, resulting in the absence of an OFF-state within V GS = −2V ~ V GS = 2V.…”

Section: Resultsmentioning

confidence: 99%

Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

Kuo

Chang

Liu

et al. 2019

Sci Rep

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In this work, we have successfully demonstrated the junctionless (JL) transistors with two-dimensional-like (2D-like) nano-sheet (NS) material, amorphous indium tungsten oxide (a-IWO), as an active channel layer. The influences of the different gate insulator (GI) materials and the scalings of GI thickness, a-IWO channel thickness, and channel lengths on the a-IWO NS JL transistors (a-IWO NS-JLTs) have been studied for the purposes of low operation voltage (gate voltage ≤2V) and high performance. The 2D-like a-IWO NS-JLTs exhibit low operation voltage, low source/drain (S/D) contact resistance (R C ) and other key electrical characteristics, such as high field-effect mobility (μ FE ), near ideal subthreshold swing (S.S.), and large ON/OFF currents ratio (I ON /I OFF ). The remarkable device characteristics also make the proposed 2D-like a-IWO NS-JLTs promising for system-on-panel (SoP) and vertically stacked (VS) hybrid CMOS applications.

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Section: Resultsmentioning

confidence: 99%

Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

Kuo

Chang

Liu

et al. 2019

Sci Rep

Self Cite

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“…[6][7][8] Gate-all-around (GAA) nanowire (NW) architecture can be well matched with poly-Si JL transistors for a reduced total number of GBs and improved subthreshold characteristics, as well as enhanced gate controllability. [9][10][11] Therefore, highperformance GAA poly-Si JL NW transistors can be obtained by suppressing the GB defects and adopting a small-size NW channel.…”

Section: Introductionmentioning

confidence: 99%

Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors

Ahn

Saraya

Kobayashi

et al. 2021

Jpn. J. Appl. Phys.

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In this paper, we experimentally examined the threshold voltage (V T) variability and the corner effects in gate-all-around p-type poly-Si junctionless (JL) nanowire (NW) and nanosheet (NS) transistors as a function of various effective channel width. The fabricated devices showed small V T variability characteristics even in poly-Si JL NW channel structure thanks to the improved quality of poly-Si channel by fluorine (F) passivation and reduced channel concentration by boron (B) segregation. In addition, it was found by examining the corner effects that the fabricated devices exhibit accumulation-mode like behaviors. The origins of these phenomena are discussed.

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“…However, this integration scheme suffers from poly-silicon roughness obtained after processing. Typical RMS values are 0.7nm [5]-1.2nm [6] (Green Nanosecond Laser Crystallization (GNS-LC) + Chemical Mechanical Polishing (CMP)) or 0.6nm [7] (HPA trimming).…”

Section: Introductionmentioning

confidence: 99%

Laser Processing For 3D Junctionless Transistor Fabrication

Bosch

Alba

Kerdilès

et al. 2019

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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To take fully advantage of Junctionless transistor (JLT) low cost and low temperature feature we investigate a 475°C process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 10 19 at/cm 3) poly-silicon film featuring excellent roughness values (R max = 1.6nm and RMS=0.2nm). Guidelines for grain size optimization with nanosecond (ns) laser annealing are given.

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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application

Cited by 18 publications

References 19 publications

Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors

Laser Processing For 3D Junctionless Transistor Fabrication

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