2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems 2013
DOI: 10.1109/vlsid.2013.215
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K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible Multiplier

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Cited by 10 publications
(1 citation statement)
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“…So far, many reversible arithmetic operators have been designed to perform addition [5][6][7][8][9][10][11][12] and multiplication [3,[13][14][15][16][17] that some of them are parity preserving and thus beneficial for fault-tolerant reversible circuits. In addition, some designs include proposing new gates and then utilizing them in the proposed adder or multiplier circuit such as [9,10,12,13] , and the others are based on exploiting the new arrangements of the existing gates.…”
Section: Introductionmentioning
confidence: 99%
“…So far, many reversible arithmetic operators have been designed to perform addition [5][6][7][8][9][10][11][12] and multiplication [3,[13][14][15][16][17] that some of them are parity preserving and thus beneficial for fault-tolerant reversible circuits. In addition, some designs include proposing new gates and then utilizing them in the proposed adder or multiplier circuit such as [9,10,12,13] , and the others are based on exploiting the new arrangements of the existing gates.…”
Section: Introductionmentioning
confidence: 99%