K longest paths per gate (KLPG) test generation for scan-based sequential circuits

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

“…1 show a fault free clock signal and the clock signal with a delay fault. We assume a typical LOC test [8], [9], where the shift clock rate is slow, and the launch and capture clock rate is fast (usually same as the system clock rate). The clock cycles in the scan-in and scan-out modes are longer than in the LOC mode.…”

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects

“…This method ignores delay variations and suffers from the need for a complex, time-consuming search procedure and robust test-generation constraints. Qui et al [14] attempt to find the k longest paths (referred to as KLPG) through the inputs and output of each gate for slow-to-rise and slow-to-fall faults. Similar to [13], a considerable amount of pre-processing is needed to search for long paths.…”

Timing-based delay test for screening small delay defects

“…The technique attempts to find the longest sensitizable path passing through the target line producing a rising (falling) transition on it. In [12], the authors proposed a new ATPG tool to generate K longest paths per gate for transition fault test. The technique targets all the transition faults to find the longest path.…”