$Ka$-Band Low-Loss and High-Isolation Switch Design in 0.13-$\mu{\hbox {m}}$ CMOS

Min, Byung-Wook; Rebeiz, Gabriel M.

doi:10.1109/tmtt.2008.921749

Cited by 90 publications

(12 citation statements)

References 18 publications

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“…Previous works have attempted to reduce parasitic capacitors by using a silicon-on-insulator (SOI) process or by adapting a switch biasing technique. Thus, resonant switch configurations using isolation enhancement (IE) inductors perform better at mm-wave frequencies [21][22][23][24]. Although the size is larger than π-network SPDT, it can be integrated, and the switch performance can be improved in certain mm-wave bands.…”

Section: Introductionmentioning

confidence: 99%

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

Park

Lee

et al. 2018

Applied Sciences

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This paper presents two single-pole, double-throw (SPDT) mm-wave switches for Ka-band phased-array transceivers, fabricated with a 65-nm complementary metal oxide semiconductor (CMOS) process. One switch employs cross-biasing (CB) control with a single supply, while the other uses dual-supply biasing (DSB) control with positive and negative voltages. Negative voltages were generated internally, using a ring oscillator and a charge pump. Identical gate and body floated N-type metal oxide semiconductor field effect transistors (N-MOSFETs) in a triple well were used as the switch core transistors. Inductors were used to improve the isolation between the transmitter (TX) and receiver (RX), as well as insertion loss, by canceling the parasitic capacitance of the switch core transistors at resonance. The size of the proposed radio frequency (RF) switch is 260 µm × 230 µm, excluding all pads. The minimum insertion losses of the CB and DSB switches were 2.1 dB at 28 GHz and 1.93 dB at 24 GHz, respectively. Between 25 GHz and 34 GHz, the insertion losses were less than 2.3 dB and 2.5 dB, the return losses were less than 16.7 dB and 17.3 dB, and the isolation was over 18.4 dB and 15.3 dB, respectively. The third order input intercept points (IIP3) of the CB and DSB switches were 38.4 dBm and 39 dBm at 28 GHz, respectively.

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Section: Introductionmentioning

confidence: 99%

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

Park

Lee

et al. 2018

Applied Sciences

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“…To overcome this problem, the gate-body floating technique is widely used in CMOS RF switch design to enhance power handling capacity. [7][8][9][10][11][12][13] The conventional π-network switch structure is adopted to increase isolation but, it is not appropriate for mmwave switch designs because the parasitic capacitances of the shunt switch are attached to the signal path. [8][9][10][11] So, an inductorbased RF switch design to resonate out the parasitic capacitance in mm-wave band has been reported.…”

Section: Introductionmentioning

confidence: 99%

“…[8][9][10][11] So, an inductorbased RF switch design to resonate out the parasitic capacitance in mm-wave band has been reported. 4,[12][13][14][15] The required inductor size becomes small enough to implement the system on chip in mm-wave band.…”

Section: Introductionmentioning

confidence: 99%

High isolation and high linearity double‐pole double‐throw CMOS switch matrix for Ka‐band wireless transceiver front‐end IC

Park

Lee

Kim

et al. 2018

Micro & Optical Tech Letters

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This letter proposes a double‐pole double‐throw (DPDT) switch with high isolation and high linearity using a 65‐nm CMOS process. To improve the isolation, resonant inductors are employed for the core switches, which are composed of a single‐stacked NMOS with gate‐body floating techniques. And, the switch is controlled by a cross‐biasing technique to increment the power linearity. The active circuits are designed separately from the passive elements to reduce the interference. The core area of the proposed switch excluding all of the pads is 380 × 300 μm2. The minimum insertion loss is 2.57 dB at 23 GHz and maximum isolation is 39.7 dB at 26 GHz, respectively. The third‐order intermodulation intercept point (IIP3) is 37 dBm at 28 GHz.

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“…Single-pole-double-throw (SPDT) switch is rather important since it can be used in various applications such as transmit/receive modules, phase shifters, attenuators and multi-standard communication systems. Thus, numbers of MMIC SPDT switches have been reported for different applications [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

“…However, they suffer from the drawbacks of relatively high cost and low integration densities. With the development of silicon-based technologies, CMOS or SiGe BiCMOS transistors-based switches have been proposed for low cost and higher integrated capacity [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A compact Ka-band SPDT switch with high isolation

Liu

Xiong³

2014

2014 International Symposium on Integrated Circuits (ISIC)

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This paper presents a Ka-band high isolation singlepole-double-throw (SPDT) switch using 0.13μm CMOS process. The switch has a measured insertion loss of 2.7-3.7 dB and an input 1-dB compression power (P 1dB ) of 8 dBm at 35 GHz. Via using the shunt NMOS topology and high quality factor match networks, 33-50 dB measured isolation is obtained within the frequency range of 30-45GHz. The switch core occupies 160 180 μm 2 chip area.Index Terms-Ka-band, SPDT, high isolation, CMOS, T/R switch.

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$Ka$-Band Low-Loss and High-Isolation Switch Design in 0.13-$\mu{\hbox {m}}$ CMOS

Cited by 90 publications

References 18 publications

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

25–34 GHz Single-Pole, Double-Throw CMOS Switches for a Ka-Band Phased-Array Transceiver

High isolation and high linearity double‐pole double‐throw CMOS switch matrix for Ka‐band wireless transceiver front‐end IC

A compact Ka-band SPDT switch with high isolation

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