Kickstarting high-performance energy-efficient manycore architectures with Epiphany

Olofsson, Andreas; Nordström, Tomas; Ul-Abdin, Zain

doi:10.1109/acssc.2014.7094761

Cited by 70 publications

(51 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Automatically generated code from the dataflow language CAL is compared with a C implementation of the 2D inverse discrete cosine transform targeting the Epiphany architecture in [23]. The development of OpenMP support has also been reported [2]. Significantly, to the best of our knowledge, no investigation has thus far reported on the use of a standard parallel programming API targeting the Epiphany architecture capable of achieving good performance for an algorithm with nontrivial parallelism.…”

Section: Related Workmentioning

confidence: 99%

“…The Epiphany architecture is scalable to 4096 cores and represents an example of an architecture designed for power-efficiency at extreme on-chip core counts. Processors based on this architecture exhibit good performance/power metrics [2] and scalability via 2D mesh network [3,4], but require a suitable programming model to fully exploit the architecture. A 16-core Epiphany III coprocessor [5] has been integrated into the Parallella mini-computer platform [6] where the RISC array is supported by a dual-core ARM CPU and asymmetric shared-memory access to off-chip global memory.…”

Section: Introductionmentioning

confidence: 99%

“…The power efficiency of the Epiphany architecture has been specifically identified as both a guide and prospective architecture for such platforms [7]. The Epiphany IV processor has a performance efficiency of 50 GFLOPS/W [2] making it one of the most efficient parallel processors based on general-purpose cores and satisfying the threshold for exascale computing with a power budget of 20 megawatts [8]. This architecture has characteristics consistent with future processor predictions arguing hundreds [9] and thousands [10,11] of cores on a chip.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Threaded MPI programming model for the Epiphany RISC array processor

Richie¹,

Ross

Park

et al. 2015

Journal of Computational Science

View full text Add to dashboard Cite

a b s t r a c tThe low-power Adapteva Epiphany RISC array processor offers high computational energy-efficiency and parallel scalability. However, extracting performance with a standard parallel programming model remains a great challenge. We present an effective programming model for the Epiphany architecture based on the Message Passing Interface (MPI) standard adapted for coprocessor offload. Using MPI exploits the similarities between the Epiphany architecture and a networked parallel distributed cluster. Furthermore, our approach enables codes written with MPI to execute on the RISC array processor with little modification. We present experimental results for matrix-matrix multiplication using MPI and highlight the importance of fast inter-core data transfers. Using MPI we demonstrate an on-chip performance of 9.1 GFLOPS with an efficiency of 15.3 GFLOPS/W. Threaded MPI exhibits the highest performance reported for the Epiphany architecture using a standard parallel programming model.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Threaded MPI programming model for the Epiphany RISC array processor

Richie¹,

Ross

Park

et al. 2015

Journal of Computational Science

View full text Add to dashboard Cite

show abstract

“…One of the results of this "merge" is the Parallella board 1 [2], created by Adapteva. It is a small (credit cardsized) board, comprising of a 16-core Epiphany coprocessor and the main dual-core ARM processor.…”

Section: Introductionmentioning

confidence: 99%

Efficient parallel execution of genetic algorithms on Epiphany manycore processor

Faber

Boryczko

2016

Annals of Computer Science and Information Systems

View full text Add to dashboard Cite

Abstract-Recent years have seen a growing trend towards the introduction of more advanced manycore processors. On the other hand, there is also a growing popularity for cheap, creditcard-sized, devices offering more and more advanced features and computational power.In this paper we evaluate Parallella -a small board with the Epiphany manycore coprocessor consisting of sixteen MIMD cores connected by a mesh network-on-a-chip. Our tests are based on classical genetic algorithms. We discuss some possible optimizations and issues that arise from the architecture of the board. Although we achieve significant speed improvements, there are issues, such us the limited local memory size and slow memory access, that make the implementation of efficient code for Parallella difficult.

show abstract

“…The Epiphany can be programmed in C/C++ and allows approaches such as Single Instruction Multiple Data (SIMD), Simple Program Multiple Data (SPMD), Multiple Instructions Multiple Data (MIMD), shared memory multithreading, message passing and several variants of dataflow programming. Consult the paper by Olofsson et al [112] for more details about Epiphany.…”

Section: Adapteva Epiphanymentioning

confidence: 99%

Algorithms and Framework for Energy Efficient Parallel Stream Computing on Many-Core Architectures

Melot¹

View full text Add to dashboard Cite

The rise of many-core processor architectures in the market answers to a constantly growing need of processing power to solve more and more challenging problems such as the ones in computing for big data. Fast computation is more and more limited by the very high power required and the management of the considerable heat produced. Many programming models compete to take profit of many-core architectures to improve both execution speed and energy consumption, each with their advantages and drawbacks. The work described in this thesis is based on the dataflow computing approach and investigates the benefits of a carefully pipelined execution of streaming applications, focusing in particular on off-and on-chip memory accesses. As case study, we implement classic and on-chip pipelined versions of mergesort for Intel SCC and Xeon. We see how the benefits of the on-chip pipelining technique are bounded by the underlying architecture, and we explore the problem of fine tuning streaming applications for many-core architectures to optimize for energy given a throughput budget. We propose a novel methodology to compute schedules optimized for energy efficiency given a fixed throughput target. We introduce Drake, derived from Schedeval, a tool that generates pipelined applications for Many-Core architectures and allows the performance testing in time or energy of their static schedule. We show that streaming applications based on Drake compete with specialized implementations and we use Schedeval to demonstrate performance differences between schedules that are otherwise considered as equivalent by a simple model. This work has been supported in parts by CUGS (the Graduate School in Computer Science, Sweden), Vetenskapsrådet, SeRC and EU FP7 EXCESS. Department of Computer and Information ScienceLinköping University SE-581 83 Linköping, Sweden Acknowledgements I would like to thank all members of PELAB for the inspiring and stimulating working environment as well as the passionate discussions around coffee or tea. In particular, my thanks to Kristian Sandahl for his efforts at maintening a strong group culture. Warm thanks to Christoph Kessler, for all fruitful discussions and ideas when my imagination came short, for his support and patience when results came late and for entrusting me with opportunities and responsibilities that taught me valuable experiences. Many thanks to Jörg Keller for sharing his ideas in details about my work, and for always carefully reviewing and challenging any hypothesis I proposed, as it repeatedly resulted in strengthening good ideas and discarding bad ones. I would like to thank all students who participated in the work, providing a precious help to progress. I am grateful to Intel for providing the Single Chip Cloud computer research prototype and their efforts to help in the numerous moments where nothing worked. Many thanks to the National Supercomputer Center (NSC) for providing powerful computing means to run my experiments, TUS for always providing a quick and precious technica...

show abstract

Kickstarting high-performance energy-efficient manycore architectures with Epiphany

Cited by 70 publications

References 9 publications

Threaded MPI programming model for the Epiphany RISC array processor

Threaded MPI programming model for the Epiphany RISC array processor

Efficient parallel execution of genetic algorithms on Epiphany manycore processor

Algorithms and Framework for Energy Efficient Parallel Stream Computing on Many-Core Architectures

Contact Info

Product

Resources

About