In this paper we introduce Epiphany as a highperformance energy-efficient manycore architecture suitable for real-time embedded systems. This scalable architecture supports floating point operations in hardware and achieves 50 GFLOPS/W in 28 nm technology, making it suitable for high performance streaming applications like radio base stations and radar signal processing. Through an efficient 2D mesh Networkon-Chip and a distributed shared memory model, the architecture is scalable to thousands of cores on a single chip. An Epiphany-based open source computer named Parallella was launched in 2012 through Kickstarter crowd funding and has now shipped to thousands of customers around the world.

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DARPA is leading a new thrust to leverage mainstream semiconductor design approaches to enable the rapid and cost-effective integration of heterogeneous device technologies. This represents a leap ahead beyond the monolithic silicon approach that has served the semiconductor industry well, but which now creates prohibitive cost and design issues at leading-edge nodes, as well as performance constraints without the benefits of broad device technology options. DARPA's Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will develop interface standards, IP reuse methodologies, and modular design approaches with the goal of making heterogeneous integration as straightforward as printed circuit board design and assembly, without compromising device performance. An overview of the program's vision, goals, and progress to date is presented here.