Kleio

Doudali, Thaleia Dimitra; Blagodurov, Sergey; Vishnu, Abhinav; Gurumurthi, Sudhanva; Gavrilovska, Ada

doi:10.1145/3307681.3325398

Cited by 42 publications

(1 citation statement)

References 18 publications

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“…Caching works no matter how well the program is made and can be used in conjunction with other approaches to improve performance. The advantage of caching in RAM on computing nodes is also influenced by the fact that RAM performance has been actively increasing in recent years, for example [41]- [44].…”

Section: Introductionmentioning

confidence: 99%

Random access memory page caching: a strategy for enhancing shared virtual memory multicomputer systems performance

Vyazigin,

Mansurova,

Malyshkin

et al. 2024

IJEECS

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This study examines a modified approach to optimizing the performance of support vector machine (SVM)-type multicomputer systems through a distinct type of caching method that allocates space in the random access memory (RAM) of a computing node for caching pages. The article extensively describes research on enhancing the performance of the SVM system through memory page caching in RAM at the hardware level by implementing the SVM system based on field-programmable gate arrays (FPGA). A systematic comparative evaluation highlights a discernible enhancement in system performance relative to systems not equipped with the revised caching algorithm. These findings could prove instrumental for subsequent studies focused on optimizing the performance of SVM systems, providing empirical data to inform future investigations and potential applications in multicomputer system performance enhancement.

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Section: Introductionmentioning

confidence: 99%

Random access memory page caching: a strategy for enhancing shared virtual memory multicomputer systems performance

Vyazigin,

Mansurova,

Malyshkin

et al. 2024

IJEECS

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Pattern-Aware Staging for Hybrid Memory Systems

Arima

Schulz

2020

Lecture Notes in Computer Science

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The ever increasing demand for higher memory performance and-at the same time-larger memory capacity is leading the industry towards hybrid main memory designs, i.e., memory systems that consist of multiple different memory technologies. This trend, however, naturally leads to one important question: how can we efficiently utilize such hybrid memories? Our paper proposes a software-based approach to solve this challenge by deploying a pattern-aware staging technique. Our work is based on the following observations: (a) the high-bandwidth fast memory outperforms the large memory for memory intensive tasks; (b) but those tasks can run for much longer than a bulk data copy to/from the fast memory, especially when the access pattern is more irregular/sparse. We exploit these observations by applying the following staging technique if the accesses are irregular and sparse: (1) copying a chunk (few GB of sequential data) from large to fast memory; (2) performing a memory intensive task on the chunk; and (3) writing it back to the large memory. To check the regularity/sparseness of the accesses at runtime with negligible performance impact, we develop a lightweight pattern detection mechanism using a helper threading inspired approach with two different Bloom filters. Our case study using various scientific codes on a real system shows that our approach achieves significant speed-ups compared to executions with using only the large memory or hardware caching: 3× or 41% speedups in the best, respectively.

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