Kosmopolitismus

Albrecht, Andrea

doi:10.1515/9783110906066

Cited by 36 publications

(4 citation statements)

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“…To verify that the proposed test generation method is capable of reducing TC numbers, it is applied to multiple circuits shown in Table II. Circuits s420, s820 and s15850 are from ISCAS89 benchmarks [28], b14, b15 and b17 are from IWLS2005 benchmarks [29], alu4, cordic and misex3 are from MCNC benchmarks [30], and the remaining circuits are from EPFL benchmarks [31]. Some details regarding TC generation shown in Fig.…”

Section: Experiments Resultsmentioning

confidence: 99%

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

He,

Lai

2024

IEICE Electron. Express

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An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000~100000 LUTs comparing with existing methods, with full fault coverage.

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Section: Experiments Resultsmentioning

confidence: 99%

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

He,

Lai

2024

IEICE Electron. Express

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“…These benchmarks consist of 69 circuits in total, including very large-scale circuits with up to twenty million nodes. In terms of open-source benchmarks, we use the EPFL [47] and IWLS [71] benchmarks, which are commonly used in previous work on LS [1], [2], [44], [72]. In terms of the industrial benchmark, we use 27 circuits from Huawei HiSilicon.…”

Section: Methodsmentioning

confidence: 99%

“…In this subsection, we evaluate the offline prediction recall, online runtime, and online optimization performance on the open-source EPFL [47] and IWLS [71] benchmarks. Due to limited space, we defer more detailed results to Appendix B.5.…”

Section: Evaluation On Open-source Benchmarksmentioning

confidence: 99%

Moisture migration tests on unsaturated expansive clays in Hefei, China

Wang

Song

et al. 2013

Applied Clay Science

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“…It is important to evaluate the proposed watermark technique on various benchmark circuits. Terefore, the evaluation of the proposed watermark techniques is carried out on EPFL [55] and IWLS [56] benchmark suites, from which the parameters such as the probability of coincidence (Pc) [57], area overhead, and latency are estimated by designing for data and delay mentioned in Case 3. Tese parameters are and summarized the table format for each circuit before and after the watermark is being integrated with it.…”

Section: Evaluation On Benchmarksmentioning

confidence: 99%

Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification

Bagul¹,

Inamdar²

2023

International Journal of Reconfigurable Computing

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As the reuse of IP cores or the development of frequently used hardware modules is gaining more attention in the semiconductor industry, the misappropriation of the owner’s identity is a rising concern. Therefore, imprinting the owner’s identity in the form of a watermark or signature on the IP core is essential to avoid intellectual property right (IPR) infringement. In view of this, a watermarking technique is proposed in the present manuscript. A constraint-based dynamic watermarking method to generate the owner’s signature is proposed in conjunction with the logic encryption-based hardware obfuscation method. The method formulated in this manuscript consciously makes use of a basic switching component for embedding a watermark with IP core and hardware obfuscation, to achieve a lower overhead budget. Through the switching mechanism, the embedded watermark can be made detectable to legitimate end users off chip via test pin. The logic encryption-based method is set for accessing the watermark. Furthermore, an encrypted functionality is set as the signature generator module for generating owner’s signature. This provides hardware obfuscation and two-stage authentication mechanism for the generation of owner’s signature, and as a result of this, double-layer protection is achieved. Furthermore, a novel method to configure input key for signature generation module and to formulate owner’s signature is proposed. The viability of the present watermark technique for real-life application is checked on the ground of transparency, security, reliability, performance overhead, and robustness. Since the watermark in the proposed method is embedded outside the IP core, it does not cause any latency for the IP core functionality. Thus, even with significantly lower area overhead (∼<1.4%), the proposed method is able to provide higher robustness in terms of lower probability of coincidence (PC = 4.68 e − 97).

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Kosmopolitismus

Cited by 36 publications

References 0 publications

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

Moisture migration tests on unsaturated expansive clays in Hefei, China

Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification

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