Lakefield: Hybrid cores in 3D Package

Khushu, Sanjeev; Gomes, Wilfred

doi:10.1109/hotchips.2019.8875641

Cited by 13 publications

(3 citation statements)

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“…Intel’s Lakefield processor combines heterogeneous 3D chip stacking with hybrid computing through Foveros [ 46 ]. As shown in Figure 7 , the Chiplets are stacked face-to-face on an active silicon adapter board.…”

Section: Chiplet-based Processing-in-memory Architecturementioning

confidence: 99%

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Tian

Zhao

et al. 2022

Micromachines

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With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the “storage wall”, it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the “storage wall” problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed.

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Section: Chiplet-based Processing-in-memory Architecturementioning

confidence: 99%

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Tian

Zhao

et al. 2022

Micromachines

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“…AMP architectures have drawn the attention of major hardware players; the ARM big.LITTLE processor [2,19] -widely extended in the mobile market segment -or the upcoming Intel Lakefield SoC [28] are clear examples of commercial AMP products. Another platform that also leverages different core types with a shared ISA, but in the high performance computing arena, is the Sunway Taihu-Light supercomputer [13,17], which led the Top500 list in 2016 and 2017.…”

Section: Introductionmentioning

confidence: 99%

Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors

Sáez

Castro

Prieto-Matías

2020

49th International Conference on Parallel Processing - ICPP

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Asymmetric multicore processors (AMPs) couple high-performance big cores and low-power small cores with the same instruction-set architecture but different features, such as clock frequency or microarchitecture. Previous work has shown that asymmetric designs may deliver higher energy efficiency than symmetric multicores for diverse workloads. Despite their benefits, AMPs pose significant challenges to runtime systems of parallel programming models. While previous work has mainly explored how to efficiently execute task-based parallel applications on AMPs, via enhancements in the runtime system, improving the performance of unmodified data-parallel applications on these architectures is still a big challenge. In this work we analyze the particular case of loop-based OpenMP applications, which are widely used today in scientific and engineering domains, and constitute the dominant application type in many parallel benchmark suites used for performance evaluation on multicore systems. We observed that conventional loop-scheduling OpenMP approaches are unable to efficiently cope with the load imbalance that naturally stems from the different performance delivered by big and small cores.To address this shortcoming, we propose Asymmetric Iteration Distribution (AID), a set of novel loop-scheduling methods for AMPs that distribute iterations unevenly across worker threads to efficiently deal with performance asymmetry. We implemented AID in libgomp -the GNU OpenMP runtime system-, and evaluated it on two different asymmetric multicore platforms. Our analysis reveals that the AID methods constitute effective replacements of the static and dynamic methods on AMPs, and are capable of improving performance over these conventional strategies by up to 56% and 16.8%, respectively. CCS CONCEPTS• Computer systems organization → Multicore architectures; Heterogeneous (hybrid) systems; • Software and its engineering → Runtime environments; Parallel programming languages.

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“…With the Intel Lake eld architecture [35] and an AMD patent [42], major vendors recently announced to introduce heterogeneous multi-core architectures in upcoming processor designs. While the approach of tightly coupling di erent processor cores on one chip to balance power and energy e ciency is already used by ARM's big.LITTLE technology [6] in mobile platforms, Intel and AMD are planning to introduce this concept in forthcoming computer architectures.…”

Section: Introductionmentioning

confidence: 99%

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment

Nasahl,

Schilling,

Werner

et al. 2020

Preprint

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To ensure secure and trustworthy execution of applications in potentially insecure environments, vendors frequently embed trusted execution environments (TEE) into their systems. Applications executed in this safe, isolated space are protected from adversaries, including a malicious operating system. TEEs are usually build by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these approaches only cover a narrow threat model resulting in limited security guarantees. Enclaves nested into the application processor typically provide weak isolation between the secure and non-secure domain, especially when considering side-channel a acks. Although external secure elements do provide strong isolation, the slow communication interface to the application processor is exposed to adversaries and restricts the use cases. Independently of the used implementation approach, TEEs o en lack the possibility to establish secure communication to external peripherals, and most operating systems executed inside TEEs do not provide state-of-the-art defense strategies, making them vulnerable against various a acks.We argue that TEEs, such as Intel SGX or ARM TrustZone, implemented on the main application processor, are insecure, especially when considering side-channel a acks. In this paper, we demonstrate how a heterogeneous multicore architecture can be utilized to realize a secure TEE design. We directly embed a secure processor into our HECTOR-V architecture to provide strong isolation between the secure and non-secure domain. e tight coupling of the TEE and the application processor enables HECTOR-V to provide mechanisms for establishing secure communication channels between di erent devices. We further introduce RISC-V Secure Co-Processor (RVSCP), a security-hardened processor tailored for TEEs. To secure applications executed inside the TEE, RVSCP provides hardware enforced control-ow integrity and rigorously restricts I/O accesses to certain execution states. RVSCP reduces the trusted computing base to a minimum by providing operating system services directly in hardware.

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Lakefield: Hybrid cores in 3D Package

Cited by 13 publications

References 0 publications

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment

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