Large dynamic range computations over small finite rings

Wigley, Neil M.; Jullien, G.A.; Reaume, D.

doi:10.1109/12.250611

Cited by 27 publications

(16 citation statements)

References 10 publications

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“…We have chosen the implementation of a modulo 7 multiplier to illustrate the results of our design process. Such a multiplier is an important building block in a certain number of theoretic techniques for implementing DSP arithmetic [34], and one of the authors has previously built the same function using "pull down" circuit blocks [13]. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…However, since they are not adjacent to each other, we make them adjacent, by switching the positions of nodes 9 and 10 and nodes 12 and 13, before applying transformation 5. The updated position list now becomes 31, 32 34 51, 52 53 Finally, we apply transformation 1 to the nonterminal nodes at level 4 and generate the nodes at the fifth level. All these nodes can be converted to terminal nodes using transformation 4.…”

Section: Example Of Ptl Synthesis With 123-ddmentioning

confidence: 99%

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Design of dynamic pass-transistor logic circuits using 123 decision diagrams

Jaekel

Bandyopadhyay

Jullien

1998

IEEE Trans. Circuits Syst. I

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Pass transistor logic (PTL) has advantages over standard CMOS designs in terms of layout density, circuit delay, and power consumption and is well suited for pipelined circuits. In this paper we develop a decision-diagram-based model, the 123-decision diagram, which can be used to efficiently synthesize PTL circuits, and we investigate multilevel logic synthesis techniques for complex, pipelined PTL networks using this model. Experiments on a large number of benchmark circuits show that PTL networks synthesized using our techniques are significantly more economic in terms of silicon area compared to those using existing techniques.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Example Of Ptl Synthesis With 123-ddmentioning

confidence: 99%

Design of dynamic pass-transistor logic circuits using 123 decision diagrams

Jaekel

Bandyopadhyay

Jullien

1998

IEEE Trans. Circuits Syst. I

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“…The reduced switching-tree multiplier modulo 7 presented in [17] consumes, 528 m 622 m in a 3-m CMOS technology or approximately 40 FA's in an 0.8-m CMOS technology, assuming that an FA requires an area of 51 m 38 m [18]. The operating frequency of the particular multiplier when implemented in a 0.8-m CMOS technology, is anticipated to increase from 40 to 150 MHz, i.e., the delay corresponds to that of 2…”

Section: A Vma Multipliers and Comparisonsmentioning

confidence: 99%

“…The benefit from adopting the MRRNS is the exploitation of the low complexity of small-modulus residue multipliers [17]. The reduced switching-tree multiplier modulo 7 presented in [17] consumes, 528 m 622 m in a 3-m CMOS technology or approximately 40 FA's in an 0.8-m CMOS technology, assuming that an FA requires an area of 51 m 38 m [18].…”

Section: A Vma Multipliers and Comparisonsmentioning

confidence: 99%

Multifunction architectures for RNS processors

Paliouras

Stouraitis

1999

IEEE Trans. Circuits Syst. II

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Novel very large-scale integration architectures and a design methodology for adder-based residue number system (RNS) processors are presented in this paper. The new architectures compute residues for more than one modulus either serially or in parallel, while their use can increase the resource utilization in a processor. Complexity is reduced by sharing common intermediate results among the various RNS moduli channels and/or operations that compose an RNS processor. The presented architectures are distinguished into two subtypes, depending on whether the inter-channel parallelism is preserved or not. The multifunction architecture paradigm is demonstrated by its application in residue multiplication, binary-to-residue conversion, quadratic RNS (QRNS) mapping, and base extension. The derived architectures are compared to previously reported equivalent ones and are found to be efficient in area 2 time product sense. Finally, the proposed design methodology reveals a new tradeoff in residue processor design, leading to more efficient RNS processors.Index Terms-Design methodology, digital signal processing, residue arithmetic.

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“…A sample of these are listed in the Residue Number Systems section of the Bibliography, Refs. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29].…”

Section: Rns Arithmeticmentioning

confidence: 99%