Laser-Induced Fault Effects in Security-Dedicated Circuits

Beroulle, Vincent; Candelier, P.; Castro, Stephan De; Natale, Giorgio Di; Dutertre, Jean-Max; Flottes, Marie-Lise; Hély, David; Hubert, G.; Leveugle, Régis; Li, Feng; Maistri, Paolo; Papadimitriou, Athanasios; Rouzeyre, Bruno; Tavernier, C.; Vanhauwaert, Pierre

doi:10.1007/978-3-319-25279-7_12

Cited by 6 publications

(4 citation statements)

References 24 publications

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“…that of CMOS bulk from a security perspective. The authors of [15], [16], [25] performed such experiments at the 28 nm technological node on elementary test transistors. Their main purpose was to build electrical models of the laser illumination of FD-SOI transistors.…”

Section: B Security Focused Experimental State-of-the-artmentioning

confidence: 99%

“…SEE laser emulation is done with settings chosen to mimic the passing of a ionizing particle through silicon [2]: a wavelength in the near Infrared (IR), a laser pulse duration in the picosecond range (from several ps to a few tens of ps), and a laser beam diameter set to 1 µm (the minimal size achievable with an air gap lens). Regarding the interest of using FD-SOI rather than CMOS bulk to mitigate laser fault injection, there are very few published papers [15], [16]. Moreover, their experimental results were as well obtained on elementary test elements.…”

Section: Introductionmentioning

confidence: 99%

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The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Dutertre

Beroulle

Candelier

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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At first used to emulate the effects of radioactive ionizing particules passing through integrated circuits (ICs), laser illumination is also used to inject faults into the computations of secure ICs for the purpose of retrieving secret data. The CMOS FD-SOI technology is expected to be less sensitive to laser faults injection than the more usual CMOS bulk technology. We report in this work an experimental assessment of the interest of using FD-SOI rather than CMOS bulk to decrease laser sensitivity. Our experiments were conducted on test chips at the 28 nm node for both technologies with laser pulse durations in the picosecond and nanosecond ranges.

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Section: B Security Focused Experimental State-of-the-artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Dutertre

Beroulle

Candelier

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…To make the system safe with respect to hardware attacks, several physical protections have been developed. Such as active shields protecting against invasive probing attacks [24], fault-tolerant redundant hardware systems [10] to prevent fault attacks, dual coil [40] or light sensors [12] to protect against electromagnetic attacks. Because of the extensive research into physical protections, we consider that they are already implemented in systems which are physically accessible to prevent physical attacks.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms

PolychronouNikolaos-Foivos

ThevenonPierre-Henri

PuysMaxime

et al. 2021

ACM Trans. Des. Autom. Electron. Syst.

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With the advances in the field of the Internet of Things (IoT) and Industrial IoT (IIoT), these devices are increasingly used in daily life or industry. To reduce costs related to the time required to develop these devices, security features are usually not considered. This situation creates a major security concern. Many solutions have been proposed to protect IoT/IIoT against various attacks, most of which are based on attacks involving physical access. However, a new class of attacks has emerged targeting hardware vulnerabilities in the micro-architecture that do not require physical access. We present attacks based on micro-architectural hardware vulnerabilities and the side effects they produce in the system. In addition, we present security mechanisms that can be implemented to address some of these attacks. Most of the security mechanisms target a small set of attack vectors or a single specific attack vector. As many attack vectors exist, solutions must be found to protect against a wide variety of threats. This survey aims to inform designers about the side effects related to attacks and detection mechanisms that have been described in the literature. For this purpose, we present two tables listing and classifying the side effects and detection mechanisms based on the given criteria.

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“…Since then, laser is considered as a very efficient tool to carry out FAs. It permits an accurate injection of faults both in space and time [2], [3], [4], [5]. Besides, despite the scaling down of IC's technologies, it was considered to be a practical means to inject faults with a high resolution (at byte or even at bit level [6]), which is mandatory to apply most of the known FA schemes [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model

Dutertre

Beroulle

Candelier

et al. 2018

2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC)

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S. Skorobogatov and R. Anderson identified laser illumination as an effective technique to conduct fault attacks in 2002. In these early days of laser-induced fault injection, it was proven to be possible to inject single-bit faults into integrated circuits. This corresponds to the more restrictive fault model found in the fault attack bibliography. The target area under laser illumination (a few micrometers, down to ∼ 1 µm) broadly matched that of a single transistor. It was consistent with a singlebit fault model. However, since then the technology of secure devices has evolved. In current circuits even the smallest laser spots may illuminate several logic cells. This raises the question of the validity of the single-bit fault model: does it still hold? In this work, we report an assessment of its validity through experimental results obtained from circuits designed at the 28 nm CMOS technology node. We also describe the main properties of the corresponding fault model obtained from both static and dynamic experiments.

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Laser-Induced Fault Effects in Security-Dedicated Circuits

Cited by 6 publications

References 24 publications

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model

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