2016
DOI: 10.1007/s11227-015-1576-8
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Last level cache size heterogeneity in embedded systems

Abstract: In typical multicore processors, Last Level Caches (LLC) are formed by distributed clusters of memory banks of the same size, namely homogeneous ones. By shutting down part of these clusters to save power along generations of multicore processors, clusters with non homogeneous cache sizes can be originated, named as heterogeneous ones. Given that heterogeneous clusters have typically smaller sizes than homogeneous ones, they present larger miss rates that are likely to deteriorate performance.In this investiga… Show more

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Cited by 6 publications
(2 citation statements)
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“…In this aspect, a series of studies combining compilation methods and specific hardware architecture features have been carried out. For example, some researchers study the register allocation algorithm on BWDSP, where the same physically numbered registers of each cluster in this architecture form a vector register, and each macro corresponds to a register with the same number 23–25 . For the GP101 processor, Hu et al 26 designed a vector register allocation algorithm under the requirement that one instruction performs the same operation on each component of a four‐dimensional vector.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…In this aspect, a series of studies combining compilation methods and specific hardware architecture features have been carried out. For example, some researchers study the register allocation algorithm on BWDSP, where the same physically numbered registers of each cluster in this architecture form a vector register, and each macro corresponds to a register with the same number 23–25 . For the GP101 processor, Hu et al 26 designed a vector register allocation algorithm under the requirement that one instruction performs the same operation on each component of a four‐dimensional vector.…”
Section: Introductionmentioning
confidence: 99%
“…For example, some researchers study the register allocation algorithm on BWDSP, where the same physically numbered registers of each cluster in this architecture form a vector register, and each macro corresponds to a register with the same number. [23][24][25] For the GP101 processor, Hu et al 26 designed a vector register allocation algorithm under the requirement that one instruction performs the same operation on each component of a four-dimensional vector. For YHFT-DSP, Tang et al 27 studied the allocation algorithm for register pairs.…”
Section: Introductionmentioning
confidence: 99%