Latchup characterization of 0.18-micron STI cobalt silicided test structures

This paper studies the matching and the stress effect problems that appear in deep submicron CMOS technologies. These effects significantly affect the electrical behavior of CMOS transistors. We propose a method to compute stress effect parameters resulting from different layout styles such as interdigitated and symmetrical styles. We apply this method to a transistor device and a differential pair device. We also quantify the errors due to transistor folding and stress effects in 65nm CMOS technology for different device layouts. The results show the effectiveness of the proposed method.

show abstract

A Python-based layout-aware analog design methodology for nanometric technologies

Youssef

Javid

Dupuis

et al. 2011

2011 IEEE 6th International Design and Test Workshop (IDT)

View full text Add to dashboard Cite

Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

show abstract

Latchup characterization of 0.18-micron STI cobalt silicided test structures

Cited by 3 publications

References 10 publications

A comprehensive geometrical and biasing analysis for latchup in 0.18-μm CoSi2 STI CMOS structure

A comprehensive geometrical and biasing analysis for latchup in 0.18-μm CoSi2 STI CMOS structure

Automatic stress effects computation based on a layout generation tool for analog IC

A Python-based layout-aware analog design methodology for nanometric technologies

Contact Info

Product

Resources

About