As the dimensions of In0.53Ga0.47As/InP double-heterojunction bipolar transistors (DHBTs) scale for terahertz applications, the DC current (β) decreases. To improve the DC performance in such scaled devices, we analyze three modified HBT geometries: a HBT with a surface pulse-doped layer in the base, a HBT having this pulse-doped layer under the emitter junction and under the base contact, but with it removed by etching in the region between the base and emitter contacts, and a device, necessarily fabricated by regrowth, in which the pulsed doped layer is present under only the base contacts. Based on a drift-diffusion/recombination model, carrier transport in the DHBT base is simulated and the corresponding β is computed using TCAD software. The structures with a pulse doped layer can attain β = 31 ∼ 39 at 100 nm emitter width. The structures with a trench between the base contact and emitter show β = 39 ∼ 54 at 100 nm emitter width. Finally, the structure with recessed base-emitter junction and regrown emitter demonstrate β = 62–119 at 100 nm emitter width.