Recent improvements in the fabrication technology of InGaAs/InP heterobipolar transistors have enabled highly scaled transistors with power gain bandwidths above 1 THz. Limitations of the conventional fabrication process that reduce RF bandwidth have been identified and mitigated, among which are high resistivity base ohmic contacts, resistive base electrodes, excessive emitter end undercut, and insufficient undercut of largediameter base posts. A novel two-step deposition process for self-aligned metallization of sub-20-nm bases has been developed and demonstrated. In the first step, a metal stack is directly evaporated onto the base semiconductor without any lithographic processing so as to minimize contamination from resist/developer chemistry. The composite metal stack exploits an ultrathin layer of platinum that controllably reacts with base, yielding low contact resistance, as well as a thick refractory diffusion barrier, which permits stable operation at high current densities and elevated temperatures. Further reduction of overall base access resistance is achieved by passivating base and emitter semiconductor surfaces in a combined atomic layer deposition Al 2 O 3 and plasma-enchanced chemical vapor depositon SiN x sidewall process. This technology enables the deposition of low-sheetresistivity base electrodes, further improving overall base access resistance and f max bandwidth. Additional process enhancements include the significant reduction of device parasitics by scaling base posts and controlling emitter end and base postundercut.

The DC current gain in In0.53Ga0.47As/InP double-heterojunction bipolar transistors is computed based on a drift-diffusion model, and is compared with experimental data. Even in the absence of other scaling effects, lateral diffusion of electrons to the base Ohmic contacts causes a rapid reduction in DC current gain as the emitter junction width and emitter-base contact spacing are reduced. The simulation and experimental data are compared in order to examine the effect of carrier lateral diffusion on current gain. The impact on current gain due to device scaling and approaches to increase current gain are discussed.

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Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (L g ) as small as 20 nm. The III-V epitaxial buffer layers were grown on 300 mm Si substrates by metal-organic chemical vapor deposition (MOCVD) and the subsequent InAlAs bottom barriers and InAs channel were grown by molecular beam epitaxy (MBE). The devices at 20 nm L g show high transconductance, ~2.0 mS/Pm at V DS =0.5V.

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