We report on the electrical characteristics of HfO 2 and HfO 2 /Al 2 O 3 gate dielectrics deposited on n-In 0.53 Ga 0.47 As by atomic layer deposition, after in-situ hydrogen or nitrogen plasma surface cleaning procedures, respectively. It is shown that alternating cycles of nitrogen plasma and trimethylaluminum prior to growth allow for highly scaled dielectrics with equivalent oxide thicknesses down to 0.6 nm and interface trap densities that are below 2.5 Â 10 12 cm À2 eV À1 near midgap. It is shown that the benefits of the nitrogen plasma surface cleaning procedure are independent of the specific dielectric. V

We report MOSFETs with 25-nm gate length (L g ), extremely thin 2.5 nm InAs channels and 0.7/3.0 nm (physical) Al 2 O x N y /ZrO 2 gate dielectrics, and 12 nm In 0.53 Ga 0.47 As vertical spacers in the raised epitaxial source/drain. The FETs establish key new DC performance records, at VLSI-relevant gate lengths (25 nm), including 0.50 mA/μm on-current (at 100 nA/μm I off and 0.5 V V DD ) and 77 mV/dec. subthreshold swing (SS) at V DS =0.5 V. At 1 μm L g and V DS =0.1 V, the minimum subthreshold swing is 61 mV/dec., a record low for InAs/InGaAs, indicating high interface quality. Introduction: InAs/InGaAs MOSFETs can provide large on-currents at low voltages, and are being investigated for VLSI application [1]- [9]. Yet, impact ionization, band-band tunneling, and source/drain (S/D) tunneling leakage currents can be high because of low bandgaps and low electron effective mass; I on (at specified low I off and V DD ), has not previously surpassed Si. Here we report 25 nm-L g ZrO 2 /InAs/InAlAs MOSFETs with performance surpassing prior III-V MOSFETs [1]-[8] and comparable to, or surpassing, leading 20-25 nm L g Si fin-[10] and nanowire [11] FETs. In these FETs, leakage currents are reduced, without substantially increasing the S/D pitch, by vertical InGaAs spacers in the raised regrown S/D [5], and by thin (2.5 nm) InAs channels for increased channel bandgap. The thin 0.7/3.0 nm (physical) Al 2 O x N y /ZrO 2 gate dielectrics [12], and the thin 2.5 nm channel together improve electrostatics, while the increased gate-channel capacitance arising from these thin layers offsets the loss in transconductance g m arising from the low mobility of the thin 2.5 nm InAs channel, with 2.38 mS/μm g m achieved at 25 nm L g . A record 0.50 mA/μm on-current (at I off =100 nA/μm and V DD =0.5 V) is achieved at a VLSI-relevant 25 nm L g . Device Fabrication: The epitaxial layer structure, grown on semi-insulating InP by solid-source MBE, has a 50 nm unintentionally doped (U.I.D) InAlAs buffer, a 250 nm 1.0×10 17 cm -3 P-type doped InAlAs barrier, a 100 nm U.I.D InAlAs barrier, a 2 nm 1.0×10 12 cm -2 N-type InAlAs pulse-doped layer, a 5 nm U.I.D InAlAs setback, a 3.5 nm InAs (strained) channel and 2 nm of the U.I.D In 0.53 Ga 0.47 spacer. To form 12-1000 nm long dummy gates, ~20 nm of HSQ was spun and patterned by e-beam lithography. To form the remainder of the vertical spacer and the N+ S/D, 10 nm U.I.D (~1.2×10 15 cm -3 ) and 60 nm Si-doped (4.0×10 19 cm -3 ) In 0.53 Ga 0.47 As were selectively regrown by MOCVD. Device mesas were isolated by wet-etch. The dummy gates were stripped in buffered HF, and ~2 nm of the In 0.53 Ga 0.47 As cap and ~1 nm of InAs channel were removed in the gate region by a 2-cycle isotropic digital etch [13], leaving a 2.5 nm InAs channel. The sample was then immediately loaded into an ALD. After in-situ N 2 plasma/TMA treatment during which ~0.7 nm of Al 2 O x N y was formed [14], a ~3 nm ZrO 2 gate dielectric was deposited [12]. The sample was then annealed in forming gas at 400°C. Ni/Au gate and Ti/Pd/A...

We demonstrate raised source/drain InAs/In 0.53 Ga 0.47 As metal-oxide-semiconductor fieldeffect-transistors incorporating a vertical spacer in the high-field region between the channel and the drain. The spacer significantly reduces off-state leakage at a high drain bias (V DS) without increasing the source/drain contact pitch. Subsequently, thinning the InAs layer within the channel further reduces the off-state leakage and subthreshold swing (SS). At $60 nm gate length and V DS ¼ 0.5 V, devices with a 6 nm/3 nm InAs/In 0.53 Ga 0.47 As channel show 2.7 mS/lm peak transconductance (g m) and 125 mV/dec SS, while devices with a 4.5 nm/3 nm InAs/In 0.53 Ga 0.47 As channel show 2.4 mS/lm peak g m and 96 mV/dec SS. V

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Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (L g ) as small as 20 nm. The III-V epitaxial buffer layers were grown on 300 mm Si substrates by metal-organic chemical vapor deposition (MOCVD) and the subsequent InAlAs bottom barriers and InAs channel were grown by molecular beam epitaxy (MBE). The devices at 20 nm L g show high transconductance, ~2.0 mS/Pm at V DS =0.5V.