Lateral PNP BJT ESD protection devices

Ващенко, В.А.; Lafonteese, D. J.; Korablev, K.

doi:10.1109/bipol.2008.4662711

Cited by 16 publications

(3 citation statements)

References 2 publications

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“…A high V hold can be achieved by decreasing current gain β of the parasitic NPN transistor [8], stacking the low-holding-voltage devices [2] or applying a non-snapback LDPMOS [4], [10] whose parasitic β is much lower than LDNMOS, but it may be damaged just after snapback as mentioned above or need more design work. Fig.…”

Section: Introductionmentioning

confidence: 99%

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Fan

Jiang

Zhang

2013

IEEE Trans. Device Mater. Relib.

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High injection electron current in an LDNMOS can lead to a strong snapback and latch-up-like characteristic. It is susceptible to latch-up-like in high-voltage ICs, if its holding voltage is lower than the power supply voltage. A method to raise the LDNMOS holding voltage is proposed and verified in a 0.35-μm 20-V/5-V BCD process without additional masks. It is realized by adding a relative high doping Nw provided for a 5-V PMOS in the drain region. The doping concentration in the Nw is higher than the injection electron density from the source under ESD stress. The Nw can extend the length of the space-charge region and lead to a higher voltage drop and high strong snapback current. This way, we get an LDNMOS with holding voltage higher than 24 V.Index Terms-ESD, high holding voltage, LDNMOS.

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Section: Introductionmentioning

confidence: 99%

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

Fan

Jiang

Zhang

2013

IEEE Trans. Device Mater. Relib.

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“…As the gate oxide thickness has decreased with succeeding technology generations, the CMOS technology circuits become more susceptible to the ESD stress. Against ESD damages, there are many ESD protection structures such as BJT, Diodes, MOS and SCR [1]. Gate-grounded MOS (ggMOS) is one of the most widely used on-chip ESD protection devices.…”

Section: Introductionmentioning

confidence: 99%

The influence of the input capacitor on the ESD behavior

Wei

Qian

Sun

et al. 2011

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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The Electrostatic discharge (ESD) capabilities of the gate-ground NMOS devices in the circuits with and without input capacitance are experimentally compared in this paper. The experimental results show that the input capacitor can reduce the ESD robustness, which has been explained in detail by using two-dimensional simulator. At last, a novel design is also proposed to improve the ESD protection behavior of the CMOS integrated circuits with the input capacitor. The proposed design is validated by using two-dimensional simulations and experimental analysis.

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“…DDSCRs not only possess as strong protection capability as one-directional SCRs, but also can realize dual-directional ESD protection with a significantly reduced chip area. However, the conventional DDSCRs still have some problems such as a low holding voltage (V h / and weak latchup immunity, limiting their practical applications as effective ESD protection devices OE3 8;10;11 .…”

Section: Introductionmentioning

confidence: 99%

Design of novel DDSCR with embedded PNP structure for ESD protection

Liang

et al. 2015

J. Semicond.

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A novel dual-directional silicon controlled rectifier (DDSCR) device with embedded PNP structure (DDSCR-PNP) is proposed for electrostatic discharge (ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage (V h /. Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP (PNP_2). Then, experimental devices are fabricated in a 0.35 m bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the V h of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width. However, the reduced leakage current (I L / of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12 m. Finally, the factors influencing V h and I L are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase V h and decrease I L . When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased I L . The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.

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Lateral PNP BJT ESD protection devices

Cited by 16 publications

References 2 publications

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

A Method to Prevent Strong Snapback in LDNMOS for ESD Protection

The influence of the input capacitor on the ESD behavior

Design of novel DDSCR with embedded PNP structure for ESD protection

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