2023
DOI: 10.1038/s41467-023-43323-x
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Lattice-mismatch-free construction of III-V/chalcogenide core-shell heterostructure nanowires

Fengjing Liu,
Xinming Zhuang,
Mingxu Wang
et al.

Abstract: Growing high-quality core-shell heterostructure nanowires is still challenging due to the lattice mismatch issue at the radial interface. Herein, a versatile strategy is exploited for the lattice-mismatch-free construction of III-V/chalcogenide core-shell heterostructure nanowires by simply utilizing the surfactant and amorphous natures of chalcogenide semiconductors. Specifically, a variety of III-V/chalcogenide core-shell heterostructure nanowires are successfully constructed with controlled shell thicknesse… Show more

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Cited by 26 publications
(11 citation statements)
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“…Meanwhile, the photoconductive detectors normally need an external power supply to achieve the desired device performance, which not only increases energy consumption, but also makes it difficult to miniaturize photodetectors. 23–27 Therefore, it is full of challenge to develop a novel structure to solve these problems.…”
Section: Introductionmentioning
confidence: 99%
“…Meanwhile, the photoconductive detectors normally need an external power supply to achieve the desired device performance, which not only increases energy consumption, but also makes it difficult to miniaturize photodetectors. 23–27 Therefore, it is full of challenge to develop a novel structure to solve these problems.…”
Section: Introductionmentioning
confidence: 99%
“…6 It is found that the lower experimental mobility arises from two intrinsic challenges: (i) metal–semiconductor interface contacts, where the presence of defect-induced gap states can suppress the carrier-injection efficiency, leading to both Fermi level pinning and Schottky barriers; 7–9 (ii) electron transport in semiconductor channels, mainly influenced by Coulomb impurities near the semiconductor–dielectric interface, charge traps, defects, etc. 10–12 Therefore, further electronic performance optimization of MoS 2 devices by reducing contact resistance, enhancing carrier transport, and improving the mobility is the central task to tackle the application challenges of transistors.…”
Section: Introductionmentioning
confidence: 99%
“…[8][9][10][11][12][13][14] Moreover, they provide the advantage of designing heterostructures without the requirement of precise atomic lattice matching, resulting in greater freedom in designing and engineering electronic and optoelectronic devices. [15][16][17][18][19][20][21][22] The use of vdW heterostructures composed of 2D crystals as tunneling transistors is a highly promising field for low-power applications. 23,24 These heterostructures allow for the manipulation of carrier densities and electron affinities, enabling the tailored design of band alignments.…”
Section: Introductionmentioning
confidence: 99%