Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

Boncalo, Oana; Kolumban-Antal, Gyorgy; Amăricăi, Alexandru; Savin, Valentin; Declercq, David

doi:10.1109/tcsi.2018.2884252

Cited by 22 publications

(15 citation statements)

References 25 publications

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“…However, this results in the loss of the gain generated by the corresponding check node, which cannot positively impact subsequent iterations. Referring to formula (8), many references [15,16,18] suggest that, in such instances, the corresponding gain can be calculated and stored in the corresponding memory space. The gain will not be read and stacked until the LLR is updated at the same position.…”

Section: Patch Methods Based On Variable-to-check Messagementioning

confidence: 99%

“…However, this approach incurs a significant performance loss compared to the theoretical layered decoding algorithm, necessitating more iterations. Similarly, the residue-based layered schedule [16] continuously accumulates and stores the contributions in registers when pipeline conflicts arise, adding them to the corresponding LLRs at the end of the pipeline problem. [17] proposes to split the matrix for the LDPC codes in the DVB-T2 protocol, which can reduce the degree of parallelism and significantly reduce the number of conflicts.…”

Section: Related Workmentioning

confidence: 99%

“…Like other works, the hardware implementation of layered decoders in [15,16,18], due to the fact that many intermediate process variables are stored in FIFO, the read order and write-back order of each layer of LLR RAM must be consistent. It causes some contradictions in the rearrangement of the reading and writing order of multi-layer overlapping submatrices.…”

Section: Inter-layer and Intra-layer Processing Schedulingmentioning

confidence: 99%

See 2 more Smart Citations

Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

Wang,

Xu,

Chen

et al. 2024

Preprint

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Pipeline conflicts arising from data dependencies are a common issue encountered in the hardware implementation of layered QC-LDPC decoders. This paper proposes an efficient layered decoding architecture to reduce pipeline conflicts without introducing stall cycles, by reordering the processing order offline and using the patch method based on variable-to-check message. The experimental results on the LDPC code of the IEEE802.16 standard in the OFDM-PON system demonstrate that the proposed architecture has a sensitivity improvement of 0.125 dBm and 0.375 dBm, respectively, compared with our previous work and the method described in the other work.

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Section: Patch Methods Based On Variable-to-check Messagementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Inter-layer and Intra-layer Processing Schedulingmentioning

confidence: 99%

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Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

Wang,

Xu,

Chen

et al. 2024

Preprint

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“…Layered Normalized Min-Sum Algorithm (LNMSA) [8] is one of the most commonly used QC-LDPC soft-decision decoding algorithms. The initial input of decoding is a Loglikelihood Ratio (LLR) value that represents channel's soft message.…”

Section: Layered Normalized Min-sum Algorithmmentioning

confidence: 99%

High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

Zhang

Lian

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In conventional Low-Density Parity-Check (LDPC) decoders, the real-time processing performance should meet its maximum decoding iterations for all packets and the work frequency or supply voltage is always fixed at a high level, which decreases its energy efficiency. In this paper, an energyefficient LDPC decoding architecture with an adaptive voltagefrequency scaling (AVFS) scheme is presented. According to the usage of input packet FIFO related to variable decoding iterations, the architecture can dynamically adjust decoder's work frequency and supply voltage to reduce the processing energy while meeting its real-time processing requirement. Finally, the decoder is implemented with 28 nm CMOS process. Experimental results show that our decoder has a throughput of 1590 Mb/s when the raw bit error rate (RBER) of Flash memory is up to 10 -2 . The power consumption of the decoder can be reduced by 25%-62% and energy efficiency can be increased to 1.3-2.5 times under different AWGN noise.

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“…The routing network is implemented with the help of barrel shifters, where, the shift factors are stored in a memory. The authors in [ 11 ] have implemented pipelined layered decoder architecture for QC-LDPC codes. A high throughput is achieved by implementing a flexible partially parallel decoder supporting different parallelism factors and a routing network supporting different matrices.…”

Section: Introductionmentioning

confidence: 99%

An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder

et al. 2021

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Area efficient and high speed forward error correcting codes decoder are the demand of many high speed next generation communication standards. This paper explores a low complexity decoding algorithm of low density parity check codes, called the min-sum iterative construction a posteriori probability (MS-IC-APP), for this purpose. We performed the error performance analysis of MS-IC-APP for a (648,1296) regular QC-LDPC code and proposed an area and throughput optimized hardware implementation of MS-IC-APP. We proposed to use the layered scheduling of MS-IC-APP and performed other optimizations at architecture level to reduce the area and to increase the throughput of the decoder. Synthesis results show 6.95 times less area and 4 times high throughput as compared to the standard min-sum decoder. The area and throughput are also comparable to the improved variants of hard-decision bit-flipping (BF) decoders, whereas, the simulation results show a coding gain of 2.5 over the best implementation of BF decoder in terms of error performance.

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Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

Cited by 22 publications

References 25 publications

Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

Efficient Pipeline Conflict Resolution for Layered QC-LDPC Decoders in OFDM-PON

High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder

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