Layout dependence of CMOS latchup

Menozzi, Roberto; Selmi, L.; Sangiorgi, E.; Crisenza, G.; Cavioni, T.; Riccò, B.

doi:10.1109/16.7402

Cited by 37 publications

(3 citation statements)

References 4 publications

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“…In bulk CMOS, using heavily doped substrates with thin epitaxial layers can greatly reduce the substrate resistance [81], and the judicious placement of substrate/well contacts or guard rings is a common cure [82].…”

Section: Single Event Latchup and Snapbackmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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Section: Single Event Latchup and Snapbackmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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“…Single event upset (SEU) where logic data is altered, and single event latch-up (SEL) where a parasitic thyristor is turned on and draws a large current, are particularly relevant. The technique to use enclosed NMOS transistors and guardrings severely reduces the risk of electricallyor radiation-induced latch-up [20][21][22]. In fact, P+ guards are in effect very good P-substrate contacts (or P-well contacts as the case may be), and good substrate (and/or well) contacts are a standard means to reduce the probability to turn on parasitic thyristors and to create a latch-up.…”

Section: Tolerance To Single Event Effectsmentioning

confidence: 99%

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10Mrad and beyond

Snoeys

Burns

Campbell

et al. 2001

Nuclear Instruments and Methods in Physics Research Section A:

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“…While analysis on layout considerations for 2D latchup has been published [4], the smaller geometries present in VLSI require 3D simulation since current flow in the third dimension is not uniform. Lateral trigger current necessary for latchup was simulated using the structure shown in Figure 2 for the N+ cathode placed in locations A (case A ) and B (case B) respectively.…”

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confidence: 99%

A STRIDE Towards Practical 3D Device Simulation - Computational and Visualization Considerations

Chin

Wu²,

Dutton³

Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits

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Although 3D device simulators have been present for a number of years [l], two major concerns have prevented them from becoming practical toolsthe large computational resources necessary to perform the simulation and the problems associated with data visualization in 3D. We have developed STRIDE (Stanford ThRee dimensional DEvice simulator) as a cost-efficient, visual-oriented tool for 3D device analysis. We have implemented STRIDE on an 16 processor Intel IPSCTM/2 and achieved 80% efficiency. An enhanced initial guess scheme as well a,s an enhanced iteration scheme result in additional performance. In addition the use of advanced 3D visualization tools provides rapid analysis of the resultsgiving insight to 3D device effects. As an example, 3D latchup is investigated.To maintain numerical stability in many device simulators, one must ramp up the voltages in small steps from zero to the initial bias conditionresulting in wasted simulation time. Table 1 shows that by using an improved one-step initial guess scheme based on one proposed by Edwards and Mock, the time spent to bias an npn transistor to any voltage between 0.2V and 0.8V is roughly equal. Note that if we had ramped the input with the discrete steps specified in the Table 1 (6 steps from 0 to O.SV), the simulation time would be 3 times longer.Due to the :strong coupling between the continuity and Poisson equations, Newton's method is often preferred over Gummels methodwith the notion that the fewer number of iterations necessary to achieve convergence overshadows the increased size of the system to solve. STRIDE, however, uses Gummel-based methods. Built upon the success of hISP schemes in one-carrier simulation [2], three schemes have been developed for two-carriers. Two of these schemes are simple extensions of one-carrier MSP, while the third scheme, MSP-2C7 solves both continuity equations simultaneously. Figure 1 shows the total amount of CPU time necessary to converge at a particular base-emitter voltage for an npn structure for both the traditional and MSP Gummel's methods. Notice that while the times are comparable under low-level injection, in the kirk-effect region, the MSP method reduces time for convergence by 54 percent over traditional Gummel. In our latch-up structure simulation, MSF'-2C is able to obtain a rate of convergence at the latch-up state that is a factor of > 2 while the traditional Gummel iterations only achieves a rate of < 3%.The visualization tools [3] allow us to obtain various perspectives of the 3D object (including perspectives from inside the object), to slice the object at arbitrary angles to provide 2D surface plots, and to arbitrarily map colors to data values. Probably the most powerful feature is the ability to render particular portions of the object solid and others translucent, giving one the perspective of looking inside the object. In addition we have the ability to run sequences of' 3D frames, or moviesallowing visualization of voltage/time dependent phenomena.While analysis on layout considerations for 2D l...

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Layout dependence of CMOS latchup

Cited by 37 publications

References 4 publications

Magnetic Random Access Memory for Embedded Computing

Magnetic Random Access Memory for Embedded Computing

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10Mrad and beyond

A STRIDE Towards Practical 3D Device Simulation - Computational and Visualization Considerations

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