Layout impact on the performance of a locally strained PMOSFET

Abstract

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L s/d ) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.Introduction PMOS transistors with epitaxial SiGe in the S/D regions are widely regarded as a viable and manufacturable way to enhance the performance up to 35% [1][2][3]. This improvement is attributed to the presence of compressive uniaxial stress in the channel and reduction in source and drain resistance. Previous studies have shown that the induced channel stress and the consequent drive current increase are dependent on various processing factors, such as recess depth, SiGe overgrowth and the channel direction [3]. However, the question remains how this technology is applicable for next generation nodes with the active area dimensions scaled down to the decananometer range. Another important issue is related to reliability of devices with high compressive uniaxial stress. In this paper, we explore the impact of layout dimensions in a PMOS transistor technology with SiGe S/D. Besides, we present initial results on reliability (TDDB and NBTI) of these devices.Device Fabrication and Design PMOS SiGe S/D devices were fabricated using the process described in [3]. The recess of the source-drain areas varied from 70 to 120nm, but the elevation of the refilled Si 0.8 Ge 0.2 is kept constant (35nm). The active area etch back process has been optimised to target the same SiGe depth independent of active area size (Fig. 1).In order to investigate the effect of layout on performance, we use the dedicated structures of Fig. 2. The first structure consists of isolated MOSFETs, surrounded by Shallow Trench Isolation, with different source-drain lengths (L s/d ) and Device Widths (W s/d ), see Fig. 2 (left), while the other one ( Fig. 2, right) contains dense poly lines with different poly-to-poly distance (L p/p ) on one big active area. Fig. 3 shows an I on /I off plot for SiGe S/D transistors with 120nm recess depth, demonstrating 65% I on improvement vs. Si reference at I off of 100nA/�m. However, this very large improvement is relevant only to wide transistors (W=1�m) with a large active area. When the source-drain length of isolated transistors (Fig. 2, left) is reduced, the volume of compressively strained SiGe in the junction regions decreases, leading to a reduced stress in the transistor channel. This is illustrated by stress simulations using the Taurus-Process simulator [4]. The simulated structure is shown in Fig. 4. The stress in the channel as a function of the source-drain length is shown in Fig. 5 for a recess depth of 30, 70 and 120nm. While for long L s/d 's, stress does not depend on the source-drain length, for L s/d below 500nm, the depen...

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

“…This in turn leads to significantly increased mobility and performance in narrow IFQW pFETs (18). On the other hand, the Si 1-y Ge y source/drain technique is known to be less effective when the poly pitch, active-area length and device width are scaled (24,25), but the technique becomes more effective for scaled gate lengths.…”

Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI)

“…However, with the decrease of the gate pitch the CESL thickness must be shrunk in order not to fill completely the space between two adjacent gates, and the overall efficiency is consequently reduced. On the other hand, the down-scaling of the Source/Drain length reduces the e-SiGe induced strain [9], and the efficiency of such local stressors tends also to drop with the technology node scaling.…”

Deposition of O atomic layers on Si(100) substrates for epitaxial Si-O superlattices: investigation of the surface chemistry

“…In Si technology, such scaling has reached its limits and the channel carrier mobility are been enhanced by using stressors [2]. The use of stressors below 45 nm technology node has saturated due to the reduced volume of the stressor dimensions [3]. Alternative channel materials like Ge and III-V materials are also being investigated, as they offer a higher bulk carrier mobility than silicon [4].…”